D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 891
![IC H8S/2363 MCU ROMLESS 128QFP](/photos/12/40/124072/d12363vf33v_sml.jpg)
D12363VF33V
Manufacturer Part Number
D12363VF33V
Description
IC H8S/2363 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12363VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12363VF33V
Manufacturer:
ST
Quantity:
67 000
Company:
Part Number:
D12363VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
D12363VF33V
Manufacturer:
RENSAS
Quantity:
20 000
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Section 23 Power-Down Modes
When the STBY pin level is driven low, a transition is made to hardware standby mode.
23.2.3
Software Standby Mode
Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in
SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral
functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM
data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O
ports, are retained. Whether the address bus and bus control signals are placed in the high-
impedance state or retain the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt
(NMI pin, or pins IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Setting the SSI bit in
SSIER to 1 enables IRQ0 to IRQ7 to be used as software standby mode clearing sources.
Clearing with an Interrupt:
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and after
the elapse of the time set in bits STS3 to STS0 in SBYCR, stable clocks are supplied to the entire
LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7 is
generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU
side or has been designated as a DTC activation source.
Clearing with the RES Pin:
When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation
starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock
oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling.
Clearing with the STBY Pin:
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev.6.00 Mar. 18, 2009 Page 831 of 980
REJ09B0050-0600
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