D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 316
![IC H8S/2363 MCU ROMLESS 128QFP](/photos/12/40/124072/d12363vf33v_sml.jpg)
D12363VF33V
Manufacturer Part Number
D12363VF33V
Description
IC H8S/2363 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12363VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Quantity
Price
Company:
Part Number:
D12363VF33V
Manufacturer:
ST
Quantity:
67 000
Company:
Part Number:
D12363VF33V
Manufacturer:
Renesas Electronics America
Quantity:
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Part Number:
D12363VF33V
Manufacturer:
RENSAS
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20 000
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Section 7 DMA Controller (DMAC)
7.5.5
Single address mode can only be specified for channel B. This mode can be specified by setting
the SAE bit in DMABCRH to 1 in short address mode.
One address is specified by MAR, and the other is set automatically to the data transfer
acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in single address mode.
Table 7.8
Register
MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is
invalid; in its place the strobe for external devices (DACK) is output.
Figure 7.9 illustrates operation in single address mode (when sequential mode is specified).
Rev.6.00 Mar. 18, 2009 Page 256 of 980
REJ09B0050-0600
23
15
Single Address Mode
DACK pin
Register Functions in Single Address Mode
ETCR
MAR
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Write
strobe
Transfer counter
Function
Destination
address
register
Read
strobe
Start address of
transfer destination
or transfer source
(Set automatically
by SAE bit; IOAR is
invalid)
Number of transfers See sections 7.5.2,
Operation
See sections 7.5.2,
Sequential Mode,
7.5.3, Idle Mode, and
7.5.4, Repeat Mode.
Strobe for external
device
Sequential Mode,
7.5.3, Idle Mode, and
7.5.4, Repeat Mode.
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