D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 206
![IC H8S/2363 MCU ROMLESS 128QFP](/photos/12/40/124072/d12363vf33v_sml.jpg)
D12363VF33V
Manufacturer Part Number
D12363VF33V
Description
IC H8S/2363 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12363VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12363VF33V
Manufacturer:
ST
Quantity:
67 000
Company:
Part Number:
D12363VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
D12363VF33V
Manufacturer:
RENSAS
Quantity:
20 000
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Section 6 Bus Controller (BSC)
6.4.2
Bus Specifications
The external space bus specifications consist of five elements: bus width, number of access states,
number of program wait states, read strobe timing, and chip select (CS) assertion period extension
states. The bus width and number of access states for on-chip memory and internal I/O registers
are fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode
is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space. With the DRAM interface and burst ROM
interface, the number of access states may be determined without regard to the setting of ASTCR.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the WAIT pin.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WTCRA and WTCRB.
From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus
width, and number of access states and program wait states) for each basic bus interface area.
Rev.6.00 Mar. 18, 2009 Page 146 of 980
REJ09B0050-0600
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