D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 109
![IC H8S/2363 MCU ROMLESS 128QFP](/photos/12/40/124072/d12363vf33v_sml.jpg)
D12363VF33V
Manufacturer Part Number
D12363VF33V
Description
IC H8S/2363 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12363VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12363VF33V
Manufacturer:
ST
Quantity:
67 000
Company:
Part Number:
D12363VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
D12363VF33V
Manufacturer:
RENSAS
Quantity:
20 000
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2.7
The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses
a subset of these addressing modes.
Arithmetic and logic operations instructions can use the register direct and immediate addressing
modes. Data transfer instructions can use all addressing modes except program-counter relative
and memory indirect. Bit manipulation instructions can use register direct, register indirect, or
absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and
BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No. Addressing Mode
1
2
3
4
5
6
7
8
2.7.1
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register which
contains the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7
and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
The register field of the instruction code specifies an address register (ERn) which contains the
address of a memory operand. If the address is a program instruction address, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment
Register indirect with pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
Addressing Modes and Effective Address Calculation
Register Direct—Rn
Register Indirect—@ERn
Symbol
Rn
@ERn
@(d:16,ERn)/@(d:32,ERn)
@ERn+
@–ERn
@aa:8/@aa:16/@aa:24/@aa:32
#xx:8/#xx:16/#xx:32
@(d:8,PC)/@(d:16,PC)
@@aa:8
Rev.6.00 Mar. 18, 2009 Page 49 of 980
REJ09B0050-0600
Section 2 CPU
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