D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 768
![IC H8S/2363 MCU ROMLESS 128QFP](/photos/12/40/124072/d12363vf33v_sml.jpg)
D12363VF33V
Manufacturer Part Number
D12363VF33V
Description
IC H8S/2363 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12363VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number:
D12363VF33V
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Section 19 Flash Memory (0.35-μm F-ZTAT Version)
19.7.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.8 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
6. If the read data is not erased, set erase mode again, and repeat the erase/erase-verify sequence
19.7.3
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased, and while the boot program is executing in boot mode. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
2. If the interrupt exception handling is started when the vector address has not been programmed
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
Rev.6.00 Mar. 18, 2009 Page 708 of 980
REJ09B0050-0600
registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn.
value greater than (y + z + α + β) ms as the WDT overflow period.
bits are B'00. Verify data can be read in longwords from the address to which a dummy write
was performed.
as before. The maximum number of repetitions of the erase/erase-verify sequence (N) must
not be exceeded.
erasing algorithm, with the result that normal operation could not be assured.
yet or the flash memory is being programmed or erased, the vector would not be read correctly,
possibly resulting in CPU runaway.
normal boot mode sequence.
Erase/Erase-Verify
Interrupt Handling when Programming/Erasing Flash Memory
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