D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 815
![IC H8S/2363 MCU ROMLESS 128QFP](/photos/12/40/124072/d12363vf33v_sml.jpg)
D12363VF33V
Manufacturer Part Number
D12363VF33V
Description
IC H8S/2363 MCU ROMLESS 128QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12363VF33V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
128-QFP
For Use With
YR0K42378FC000BA - KIT EVAL FOR H8S/2378
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12363VF33V
Manufacturer:
ST
Quantity:
67 000
Company:
Part Number:
D12363VF33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
D12363VF33V
Manufacturer:
RENSAS
Quantity:
20 000
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(2)
The procedures for download, initialization, and programming are shown in figure 20.11.
The procedure program must be executed in an area other than the flash memory to be
programmed. Especially the part where the SCO bit in FCCS is set to 1 for downloading must be
executed in the on-chip RAM.
Programming Procedure in User Program Mode
Set the FPEFEQ, FUBRA
JSR FTDAR setting + 32
Select on-chip program
to be downloaded and
destination by FTDAR
procedure program
Set SCO to 1 and
execute download
Start programming
Set FKEY to H'A5
specify download
Clear FKEY to 0
DPFR = 0?
Initialization
FPFR = 0?
parameter
a
Yes
Yes
Initialization error processing
Download error processing
Figure 20.11 Programming Procedure
No
No
1.
2.
3.
4.
5.
6.
7.
8.
Section 20 Flash Memory (0.18-μm F-ZTAT Version)
Rev.6.00 Mar. 18, 2009 Page 755 of 980
No
JSR FTDAR setting + 16
JSR FTDAR setting + 16
Disable interrupts and bus
Set parameters to ER1
Programming finished
(FMPAR and FMPDR)
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
master operation
programming is
other than CPU
Programming
Required data
FPFR = 0?
FPFR = 0?
processing
completed?
and ER0
a
Yes
Yes
Yes
REJ09B0050-0600
Clear FKEY and
Clear FKEY and
error processing
error processing
No
No
programming
programming
9.
10.
11.
12.
13.
14.
15.
16.
17.
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