D12363VF33V Renesas Electronics America, D12363VF33V Datasheet - Page 357

• Manufacturer Part Number: D12363VF33V
• Description: IC H8S/2363 MCU ROMLESS 128QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12363VF33V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 128-QFP
• For Use With: YR0K42378FC000BA - KIT EVAL FOR H8S/2378
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8.2.2
MRB selects the DTC operating mode.
8.2.3
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
8.2.4
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
Bit
7
6
5
4
to
0
Bit Name
CHNE
DISEL
CHNS
−
DTC Mode Register B (MRB)
DTC Source Address Register (SAR)
DTC Destination Address Register (DAR)
Initial Value
Undefined
Undefined
Undefined
Undefined
R/W
−
−
−
−
Description
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 8.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers,
clearing of the activation source flag, and clearing of
DTCER is not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
Section 8 Data Transfer Controller (DTC)
Rev.6.00 Mar. 18, 2009 Page 297 of 980
REJ09B0050-0600