MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 950

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.54 Port J Data Register (PTJ)
Read: Anytime.
Write: Anytime.
Port J pins 7–4 and 2–0 are associated with the CAN4, SCI2, IIC0, the routed CAN0 modules and chip
select signals (CS0, CS1, CS2, CS3). These pins can be used as general purpose I/O when not used with
any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
952
Function
Routed
CAN4
CAN0
PJ[7:6]
Reset
Field
SCI2
PJ2
PJ1
PJ0
7–6
IIC0
Alt.
2
1
0
W
R
TXCAN4
TXCAN0
SCL0
PTJ7
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general
purpose I/O function if the CAN4 module is enabled.
The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured
as open drain outputs. Refer to IIC section for details.
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if
the routed CAN0 module is enabled. Refer to MSCAN section for details.
The chip select function (CS1) takes precedence over the general purpose I/O.
The SCI2 function takes precedence over the general purpose I/O function if the SCI2 module is enabled. Refer
to SCI section for details.
The chip select (CS3) takes precedence over the general purpose I/O function.
0
7
= Unimplemented or Reserved
RXCAN4
RXCAN0
SDA0
PTJ6
0
6
Figure 23-56. Port J Data Register (PTJ)
Table 23-51. PTJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
PTJ5
CS2
0
5
PTJ4
CS0
0
4
Description
0
0
3
PTJ2
CS1
0
2
Freescale Semiconductor
TXD2
PTJ1
0
1
RXD2
PTJ0
CS3
0
0