MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 663
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
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Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
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18.3.2.5
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.Write: Refer to each bit description. In emulation modes write
operations will also be directed to the external bus.
EROMON and ROMON control the visibility of the Flash in the memory map for CPU or BDM (not for
XGATE). Both local and global memory maps are affected.
Freescale Semiconductor
Address: 0x0013 PRR
EROMON
ROMHM
ROMON
Reset
Field
2
1
0
W
R
Enables emulated Flash or ROM memory in the memory map
Write: Never
This bit is used in some modes to define the placement of the Emulated Flash or ROM (Refer to
0 Disables the emulated Flash or ROM in the memory map.
1 Enables the emulated Flash or ROM in the memory map.
FLASH or ROM only in higher Half of Memory Map
Write: Once in normal and emulation modes and anytime in special modes
0 The fixed page of Flash or ROM can be accessed in the lower half of the memory map. Accesses to
1 Disables access to the Flash or ROM in the lower half of the memory map.These physical locations of the
Enable FLASH or ROM in the memory map
Write: Once in normal and emulation modes and anytime in special modes.
This bit is used in some modes to define the placement of the ROM (Refer to
0 Disables the Flash or ROM from the memory map.
1 Enables the Flash or ROM in the memory map.
MMC Control Register (MMCCTL1)
0
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
0x4000–0x7FFF will be mapped to 0x7F_4000-0x7F_7FFF in the global memory space.
Flash or ROM can still be accessed through the program page window. Accesses to 0x4000–0x7FFF will be
mapped to 0x14_4000-0x14_7FFF in the global memory space (external access).
= Unimplemented or Reserved
0
0
6
Figure 18-10. MMC Control Register (MMCCTL1)
Table 18-10. MMCCTL1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
;automatically select direct mode.
CAUTION
0
0
4
Description
0
0
3
Chapter 18 Memory Mapping Control (S12XMMCV3)
EROMCTL
EROMON
2
Table
18-11)
ROMHM
0
1
Table
ROMCTL
ROMON
18-11)
0
663
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