MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 88

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.3.2.5
This register enables CRG interrupt requests.
Read: Anytime
Write: Anytime
88
LOCKIE
Reset
SCMIE
Field
RTIE
ILAF
7
6
4
1
W
R
1. ILAF is set to 1 when an illegal address reset occurs. Unaffected by system reset. Cleared by power on or low
voltage reset.
RTIE
Real Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
Illegal Address Reset Flag — ILAF is set to 1 when an illegal address reset occurs. Refer to S12XMMC Block
Guide for details. This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Illegal address reset has not occurred.
1 Illegal address reset has occurred.
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
Self ClockMmode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
CRG Interrupt Enable Register (CRGINT)
0
7
= Unimplemented or Reserved
ILAF
6
1
Figure 2-8. CRG Interrupt Enable Register (CRGINT)
Table 2-3. CRGINT Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
LOCKIE
0
4
Description
0
0
3
0
0
2
SCMIE
Freescale Semiconductor
0
1
0
0
0