MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 181

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.4.2
This subsection explains some of the digital features in more detail. See register descriptions for all details.
5.4.2.1
The external trigger feature allows the user to synchronize ATD conversions to the external environment
events rather than relying on software to signal the ATD module when ATD conversions are to take place.
The external trigger signal (out of reset ATD channel 7, configurable in ATDCTL1) is programmable to
be edge or level sensitive with polarity control.
combinations of control bits and their effect on the external trigger function.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when the trigger is received. In both
cases, the maximum latency time is one bus clock cycle plus any skew or delay introduced by the trigger
circuitry.
Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be
triggered externally.
If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion
sequence, this does not constitute an overrun; therefore, the flag is not set. If the trigger is left asserted in
level mode while a sequence is completing, another sequence will be triggered immediately.
Freescale Semiconductor
Digital Sub-Block
External Trigger Input
The conversion results for the external trigger ATD channel 7 have no
meaning while external trigger mode is enabled.
ETRIGLE
X
X
0
0
1
1
ETRIGP
X
X
0
1
0
1
Table 5-23. External Trigger Control Bits
MC9S12XDP512 Data Sheet, Rev. 2.21
ETRIGE
0
0
1
1
1
1
Table 5-23
NOTE
SCAN
0
1
X
X
X
X
gives a brief description of the different
Ignores external trigger. Performs one
conversion sequence and stops.
Ignores external trigger. Performs
continuous conversion sequences.
Falling edge triggered. Performs one
conversion sequence per trigger.
Rising edge triggered. Performs one
conversion sequence per trigger.
Trigger active low. Performs
continuous conversions while trigger
is active.
Trigger active high. Performs
continuous conversions while trigger
is active.
Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
Description
181