MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 557
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
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Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
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14.2
Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply
voltages, most signals are power supply signals connected to pads.
14.2.1
Signal V
this pin. A chip external decoupling capacitor (>=100 nF, X7R ceramic) between V
is not available V
For entering Shutdown Mode, pin V
14.2.2
Signals V
regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (>=100 nF, X7R ceramic) between V
supply.
14.2.3
Signals V
These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).
In Shutdown Mode an external supply driving V
Freescale Semiconductor
Table 14-1
DDR
External Signal Description
DDA
DD
shows all signals of VREG_3V3 associated with pins.
VDDR — Regulator Power Input Pins
VDDA, VSSA — Regulator Reference Supply Pins
VDD, VSS — Regulator Output1 (Core Logic) Pins
/V
is the power input of VREG_3V3. All currents sourced into the regulator loads flow through
/V
Check device level specification for connectivity of the signals.
SS
SSA,
V
SS
are the primary outputs of VREG_3V3 that provide the power supply for the core logic.
REGEN
) can smooth ripple on V
V
which are supposed to be relatively quiet, are used to supply the analog parts of the
V
Name
V
V
V
DDPLL
V
SSPLL
V
DDR
DDA
SSA
DD
SS
(optional)
Power input (positive supply)
Quiet input (positive supply)
Quiet input (ground)
Primary output (positive supply)
Primary output (ground)
Secondary output (positive supply)
Secondary output (ground)
Optional Regulator Enable
MC9S12XDP512 Data Sheet, Rev. 2.21
DDR
Table 14-1. Signal Properties
should also be tied to ground on devices without VREGEN pin.
DDR
Function
DDA
DD
.
NOTE
/V
and V
SS
can replace the voltage regulator.
SSA
can further improve the quality of this
Chapter 14 Voltage Regulator (S12VREG3V3V5)
Reset State
—
—
—
—
—
—
—
—
DDR
Pull Up
—
—
—
—
—
—
—
—
and V
SSR
(if V
SSR
557
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