MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 791

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.2
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
This register is used to configure the external access stretch (wait) function.
Freescale Semiconductor
EXSTR[2:0]
EWAITE
Reset
Field
2–0
7
W
R
EWAITE
External Wait Enable — This bit enables the external access stretch function using the external EWAIT input
pin. Enabling this feature may have effect on the minimum number of additional stretch cycles (refer to
Table
External wait feature is only active if enabled in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
0 External wait is disabled
1 External wait is enabled
External Access Stretch Bits 2, 1, 0 — This three bit field determines the amount of additional clock stretch
cycles on every access to the external address space as shown in
cycles depends on the EWAITE setting.
Stretch cycles are added as programmed in normal expanded mode and emulation expanded mode; function
not available in all other operating modes.
External Bus Interface Control Register 1 (EBICTL1)
0
7
21-6).
Figure 21-4. External Bus Interface Control Register 1 (EBICTL1)
= Unimplemented or Reserved
EXSTR[2:0]
0
0
000
001
010
011
100
101
110
111
6
Table 21-6. External Access Stretch Bit Definition
Table 21-5. EBICTL1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
EWAITE = 0
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
1 cycle
0
0
4
Number of Stretch Cycles
Description
0
0
3
Chapter 21 External Bus Interface (S12XEBIV2)
Table
EWAITE = 1
>= 2 cycles
>= 2 cycles
>= 3 cycles
>= 4 cycles
>= 5 cycles
>= 6 cycles
>= 7 cycles
>= 8 cycles
EXSTR2
21-6. The minimum number of stretch
1
2
EXSTR1
1
1
EXSTR0
1
0
793