MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 727

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4.6.1
External tagging using the external TAGHI and TAGLO pins can only be used to tag CPU opcodes; tagging
of XGATE code using these pins is not possible. An external tag triggers the state sequencer into State0
when the tagged opcode reaches the execution stage of the instruction queue.
The pins operate independently, thus the state of one pin does not affect the function of the other. External
tagging is possible in emulation modes only. The presence of logic level 0 on either pin at the rising edge
of the external clock (ECLK) performs the function indicated in the
bytes of an instruction word. If a taghit comes from the low or high byte, a breakpoint generated according
to the DBGBRK and BDM bits in DBGC1. Each time TAGHI or TAGLO are low on the rising edge of
ECLK, the old tag is replaced by a new one
19.4.7
It is possible to select breakpoints to the XGATE and let the CPU continue operation, setting DBGBRK[0],
or breakpoints to the CPU and let the XGATE continue operation setting, DBGBRK[1], or a breakpoint to
both CPU and XGATE, setting both bits DBGBRK[1:0].
There are several ways to generate breakpoints to the XGATE and CPU modules.
19.4.7.1
The XGATE software breakpoint instruction BRK can request an CPU breakpoint, via the DBG module.
In this case, if the XGSBPE bit is set, the DBG module immediately generates a forced breakpoint request
to the CPU, the state sequencer is returned to state0 and tracing, if active, is terminated. If configured for
begin-trigger and tracing has not yet been triggered from another source, the trace buffer contains no new
information. Breakpoint requests from the XGATE module do not depend upon the state of the DBGBRK
or ARM bits in DBGC1. They depend solely on the state of the XGSBPE and BDM bits. Thus it is not
necessary to ARM the DBG module to use XGATE software breakpoints to generate breakpoints in the
CPU program flow, but it is necessary to set XGSBPE. Furthermore if a breakpoint to BDM is required,
the BDM bit must also be set. When the XGATE requests an CPU breakpoint, the XGATE program flow
stops by default, independent of the DBG module. The user can thus determine if an XGATE breakpoint
has occurred by reading out the XGATE program counter over the BDM interface.
Freescale Semiconductor
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Through XGATE software breakpoint requests.
From comparator channel triggers to final state.
Using software to write to the TRIG bit in the DBGC1 register.
From taghits generated using the external TAGHI and TAGLO pins.
Breakpoints
External Tagging using TAGHI and TAGLO
XGATE Software Breakpoints
TAGHI
MC9S12XDP512 Data Sheet, Rev. 2.21
1
1
0
0
Table 19-43. Tag Pin Function
TAGLO
1
0
1
0
Both bytes
High byte
Low byte
No tag
Tag
Table
Chapter 19 S12X Debug (S12XDBGV2) Module
19-43. It is possible to tag both
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