MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 1170
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
1172
Clock Register
Written
Check
Address, Data,
Access Error and
Protection Violation
Check
Simultaneous
Multiple Flash Block
Decision
Bit Polling for
Command Completion
Check
Erase Verify
Command
Buffer Empty Check
Status
Read: FCLKDIV register
1.
2.
3.
Figure 28-25. Example Erase Verify Command Flow
yes
START
Write: Flash Block Address
Write: FCMD register
Erase Verify Command 0x05
Write: FSTAT register
Clear CBEIF 0x80
FDIVLD
and Dummy Data
Set?
Read: FSTAT register
Read: FSTAT register
MC9S12XDP512 Data Sheet, Rev. 2.21
yes
ACCERR/
no
yes
yes
CBEIF
BLANK
no
Write: FCLKDIV register
Block?
CCIF
Set?
Set?
PVIOL
Set?
Flash
EXIT Flash Block
Set?
Next
no
Erased
yes
no
yes
no
no
Write: FSTAT register
Clear ACCERR/PVIOL 0x30
Decrement Global Address
by 128K (skip unimplemented Flash)
NOTE: FCLKDIV needs to
be set once after each reset.
EXIT
Flash Block
Not Erased
Freescale Semiconductor
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