MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 1029
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.0.7
24.0.7.1
The BKGD pin is associated with the S12X_BDM and S12X_EBI modules. During reset, the
BKGD pin is used as MODC input.
24.0.7.2
Port A pins PA[7:0] and Port B pins PB[7:0] can be used for either general-purpose I/O.
24.0.7.3
Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2
output running at the core clock rate. The clock output is always enabled in emulation modes.
Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK
output running at the bus clock rate or at the programmed divided clock rate. The clock output is
always enabled in emulation modes.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-
sensitive IRQ interrupt input. IRQ will be enabled by setting the IRQEN configuration bit
(Section 24.0.5.10, “IRQ Control Register
code register. It is inhibited at reset so this pin is initially configured as a simple input with a pull-
up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ
interrupt input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It
is inhibited at reset so this pin is initially configured as a high-impedance input with a pull-up.
24.0.7.4
Port K pins PK[7:0] can be used for either general-purpose I/O.
of Modules
Number
5
4
3
2
1
Ports
BKGD Pin
Port A and B
Port E
Port K
CAN0
Table 24-61. Module Implementations on Derivatives
yes
yes
yes
yes
yes
CAN1
yes
yes
yes
—
—
MSCAN Modules
CAN2
(IRQCR)”) and clearing the I-bit in the CPU’s condition
yes
yes
—
—
—
CAN3
yes
—
—
—
—
CAN4
yes
yes
yes
yes
—
SPI0
yes
yes
yes
—
—
SPI Modules
SPI1
yes
yes
—
—
—
SPI2
yes
—
—
—
—
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