MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 613
![IC MCU 512K FLASH 144-LQFP](/photos/12/38/123875/mc9s12xa512cag_sml.jpg)
MC9S12XA512CAG
Manufacturer Part Number
MC9S12XA512CAG
Description
IC MCU 512K FLASH 144-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Specifications of MC9S12XA512CAG
Core Processor
HCS12X
Core Size
16-Bit
Speed
80MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
119
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Processor Series
S12XA
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
119
Number Of Timers
12
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12XDP512E
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 24 Channel)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale
Quantity:
490
Company:
Part Number:
MC9S12XA512CAG
Manufacturer:
Freescale Semiconductor
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Chapter 17
Memory Mapping Control (S12XMMCV2)
17.1
This section describes the functionality of the module mapping control (MMC) sub-block of the S12X
platform. The block diagram of the MMC is shown in
The MMC module controls the multi-master priority accesses, the selection of internal resources and
external space. Internal buses including internal memories and peripherals are controlled in this module.
The local address space for each master is translated to a global memory space.
17.1.1
The main features of this block are:
17.1.2
This subsection lists and briefly describes all operating modes supported by the MMC.
17.1.2.1
1. Resources are also called targets.
Freescale Semiconductor
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Paging capability to support a global 8 Mbytes memory address space
Bus arbitration between the masters CPU, BDM, and XGATE
Simultaneous accesses to different resources
Resolution of target bus access collision
Access restriction control from masters to some targets (e.g., RAM write access protection for user
specified areas)
MCU operation mode control
MCU security control
Separate memory map schemes for each master CPU, BDM, and XGATE
ROM control bits to enable the on-chip FLASH or ROM selection
Port replacement registers access control
Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes
Run mode
MMC is functional during normal run mode.
Introduction
Features
Modes of Operation
Power Saving Modes
MC9S12XDP512 Data Sheet, Rev. 2.21
1
(internal, external, and peripherals) (see
Figure
1-1.
Figure
1-1)
613
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