MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 1011

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDRP[7:0]
Reset
Reset
24.0.5.36 Port P Data Direction Register (DDRP)
Read: Anytime.
Write: Anytime.
This register configures each port P pin as either input or output.
If the associated PWM channel or SPI module is enabled this register has no effect on the pins.
The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–
0 channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM
section for details.
If SPI is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are
disabled.
Field
24.0.5.37 Port P Reduced Drive Register (RDRP)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each port P output pin as either full or reduced. If the
port is used as input this bit is ignored.
7–0
W
W
R
R
DDRP7
RDRP7
Data Direction Port P
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
on PTP or PTIP registers, when changing the DDRP register.
DDRP6
RDRP6
0
0
6
6
Figure 24-39. Port P Reduced Drive Register (RDRP)
Figure 24-38. Port P Data Direction Register (DDRP)
Table 24-35. DDRP Field Descriptions
DDRP5
RDRP5
5
0
5
0
DDRP4
RDRP4
0
0
4
4
Description
DDRP3
RDRP3
3
0
3
0
DDRP2
RDRP2
0
0
2
2
DDRP1
RDRP1
1
0
1
0
DDRP0
RDRP0
0
0
0
0