MC9S12XA512CAG Freescale Semiconductor, MC9S12XA512CAG Datasheet - Page 693

• Manufacturer Part Number: MC9S12XA512CAG
• Description: IC MCU 512K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XA512CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XA
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, I2C, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 119
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 24 Channel)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XGATE activity can still be compared, traced and can be used to generate a breakpoint to the XGATE
module. When the CPU enters active BDM mode through a BACKGROUND command, with the DBG
module armed, the DBG remains armed.
The DBG module tracing is disabled if the MCU is secure. Breakpoints can however still be generated if
the MCU is secure.
19.1.4
Figure 19-1
19.2
The DBG sub-module features two external tag input signals (see
(DUG) for the mapping of these signals to device pins. These tag pins may be used for the external tagging
in emulation modes only
Freescale Semiconductor
Enable
BDM
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
CPU BUS
XGATE BUS
0
0
1
1
x
READ TRACE DATA (DBG READ DATA BUS)
External Signal Description
Block Diagram
Active
shows a block diagram of the debug module.
BDM
x
0
1
0
1
Secure
MCU
1
0
0
0
0
COMPARATOR C
COMPARATOR D
COMPARATOR A
COMPARATOR B
Table 19-1. Mode Dependent Restriction Summary
Comparator Matches
Figure 19-1. Debug Block Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
XGATE only
Enabled
Yes
Yes
Yes
MATCH0
MATCH1
MATCH2
MATCH3
Active BDM not possible when not enabled
CONTROL
Breakpoints
XGATE only
TRIGGER
Only SWI
Possible
LOGIC
TAG &
Yes
Yes
Table
Chapter 19 S12X Debug (S12XDBGV2) Module
TRIGGER
STATE
19-2). See Device User Guide
BREAKPOINT REQUESTS
XGATE only
Possible
Tagging
CPU & XGATE
Yes
Yes
Yes
TAGS
BUFFER
SEQUENCER
TRACE
STATE
TRACE
CONTROL
TRIGGER
XGATE only
Possible
Tracing
Yes
Yes
No
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