R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 524

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 494 of 583
30.4.2
Notes:
1. To set this bit to 1, first write 0 and then 1 immediately. Do not generate an interrupt between writing 0 and
2. Write to the FMSTP bit by a program transferred to the RAM. The FMSTP bit is enabled when the FMR01 bit is
3. The CMDRST bit is enabled when the FMR01 bit is set to 1 (CPU rewrite mode enabled) and the FST7 bit in the
FMR01 Bit (CPU Rewrite Mode Select Bit)
FMR02 Bit (EW1 Mode Select Bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 01B4h
writing 1.
set to 1 (CPU rewrite mode enabled). To set the FMSTP bit to 1 (flash memory stops), set it when the FST7 bit in
the FST register is set to 1 (ready).
FST register is set to 0 (busy).
When the FMR01 bit is set to 1 (CPU rewrite mode enabled), the MCU is made ready to accept software
commands.
When the FMR02 bit is set to 1 (EW1 mode), EW1 mode is selected.
Symbol RDYSTIE BSYAEIE CMDERIE CMDRST FMSTP
CMDERIE Erase/write error interrupt enable bit
RDYSTIE Flash ready status interrupt enable bit 0: Flash ready status interrupt disabled
CMDRST Erase/write sequence reset bit
BSYAEIE Flash access error interrupt enable bit 0: Flash access error interrupt disabled
Bit
Symbol
FMSTP
FMR01
FMR02
Flash Memory Control Register 0 (FMR0)
—
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
0
Reserved bit
CPU rewrite mode select bit
EW1 mode select bit
Flash memory stop bit
b6
0
Nov 05, 2008
Bit Name
b5
0
(1)
(2)
(1)
b4
(3)
0
Set to 0.
0: CPU rewrite mode disabled
1: CPU rewrite mode enabled
0: EW0 mode
1: EW1 mode
0: Flash memory operates
1: Flash memory stops
When the CMDRST bit is set to 1, the erase/write
sequence is reset and erasure/writing can be
forcibly stopped.
When read, the content is 0.
0: Erase/write error interrupt disabled
1: Erase/write error interrupt enabled
1: Flash access error interrupt enabled
1: Flash ready status interrupt enabled
(Low-power consumption state, flash memory
b3
initialization)
0
FMR02
b2
0
Function
FMR01
b1
0
b0
—
0
30. Flash Memory
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W