R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 417

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 387 of 583
Figure 24.12
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
RDRF bit in
SSSR register
RSSTP bit in
SSCRH register
Processing
by program
Processing
by program
• CPHS bit = 0 (data download at even edges), CPOS bit = 0 (“H” when clock stops), and BS3
• CPHS bit = 1 (data download at odd edges), CPOS bit = 0 (“H” when clock stops), and BS3 to
to BS0 = 1000b (8 bits)
BS0 = 1000b (8 bits)
(output)
(output)
SSCK
SSCK
SCS
SCS
SSI
SSI
Example of Synchronous Serial Communication Unit Operation during Data
Reception (4-Wire Bus Communication Mode, 8-Bit SSU Data Transfer Length)
Preliminary specification
Specifications in this manual are tentative and subject to change.
1
0
1
0
1
0
1
0
BS0 to BS3: Bits in SSBR register
CPHS and CPOS: Bits in SSMR register
Dummy read in
SSRDR register
Dummy read in
SSRDR register
b7
Nov 05, 2008
b7
1 frame
RXI interrupt request
is generated
RXI interrupt request
is generated
1 frame
b0
Data read in SSRDR
register
Data read in SSRDR
register
b0
b7
b7
24. Synchronous Serial Communication Unit (SSU)
1 frame
RXI interrupt request
is generated
RXI interrupt request
is generated
1 frame
b0
b0
Set RSSTP
bit to 1
Set RSSTP
bit to 1
b7
b7
Data read in SSRDR
register
Data read in SSRDR
register
RXI interrupt request
is generated
RXI interrupt request
is generated
High-impedance
b0
High-impedance
b0