R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 455
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 425 of 583
25.8
Figure 25.21
Table 25.7
1Tcyc = 1/f1(s)
When the I
•
•
Therefore, the SCL signal is monitored and communication is synchronized bit by bit.
Figure 25.21 shows the Bit Synchronization Circuit Timing and Table 25.7 lists the Time between Changing SCL
Signal from “L” Output to High-Impedance and Monitoring SCL Signal.
The SCL signal is driven L level by a slave device
The rise speed of the SCL signal is reduced by a load (load capacity or pull-up resistor) on the SCL line.
Bit Synchronization Circuit
CKS3
2
C bus interface is set to master mode, the high-level period may become shorter if:
0
1
Bit Synchronization Circuit Timing
Monitoring SCL Signal
Preliminary specification
Specifications in this manual are tentative and subject to change.
Time between Changing SCL Signal from “L” Output to High-Impedance and
ICCR1 Register
SCL monitor timing
Reference clock of
Internal SCL
Nov 05, 2008
SCL
CKS2
0
1
0
1
VIH
7.5Tcyc
19.5Tcyc
17.5Tcyc
41.5Tcyc
SCL Monitoring Time
25. I
2
C bus Interface
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