R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 188

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 158 of 583
14.2
14.2.1
Note:
14.2.2
Note:
14.2.3
b7 to b0 Writing 00h and then FFh to this register initializes the watchdog timer.
b7 to b0 A write instruction to this register starts the watchdog timer.
1. The PM12 bit is set to 1 when 1 is written by a program (and remains unchanged even if 0 is written to it).
1. Write the WDTR register during the count operation of the watchdog timer.
After Reset
After Reset
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Bit
Bit
Address 0005h
Address 000Dh
Address 000Eh
This bit is automatically set to 1 when the CSPRO bit in the CSPR register is set to 1 (count source protection
mode enabled).
Set the PRC1 bit in the PRCR register to 1 (write enabled) before rewriting the PM1 register.
Symbol
Symbol
Symbol
Registers
Symbol
The initial value of the watchdog timer is specified by bits WDTUFS0 and WDTUF1 in the OFS2
register.
Bit
Bit
Bit
PM12
Processor Mode Register 1 (PM1)
Watchdog Timer Reset Register (WDTR)
Watchdog Timer Start Register (WDTS)
—
—
—
—
—
—
—
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
b7
b7
—
—
—
X
X
0
(1)
Reserved bits
WDT interrupt/reset switch bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
Reserved bit
b6
b6
b6
—
—
—
X
X
0
Nov 05, 2008
Bit Name
b5
—
b5
—
b5
—
X
X
0
b4
b4
b4
—
—
—
X
X
0
Set to 0.
0: Watchdog timer interrupt
1: Watchdog timer reset
Set to 0.
Function
Function
b3
b3
b3
—
—
—
0
X
X
PM12
b2
b2
b2
—
—
X
X
0
Function
(1)
b1
b1
b1
—
—
—
X
X
0
b0
b0
b0
—
—
—
X
X
0
14. Watchdog Timer
R/W
R/W
R/W
R/W
R/W
R/W
—
W
W