R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 542
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 512 of 583
Figure 30.13
30.4.11.6 Read Lock Bit Status Command
This command is used to read the lock bit status of any address in the program ROM area.
When 71h written in the first bus cycle and D0h is written in the second cycle to the starting block address, the
lock bit status of the specified block is stored in the LBDATA bit in the FST register. After the FST7 bit in the
FST register has been set to 1 (ready), read the LBDATA bit.
Figure 30.13 shows a Read Lock Bit Status Flowchart.
Write the command code 71h
Write D0h to the starting
block address
Preliminary specification
Specifications in this manual are tentative and subject to change.
Read Lock Bit Status Flowchart
Block not locked
LBDATA = 1?
FST7 = 1?
Start
Yes
Yes
Nov 05, 2008
No
No
Block locked
LBDATA, FST7: Bits in FST register
30. Flash Memory
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