R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 470

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 440 of 583
26.5
Table 26.2
Synch Break detection
Completion of Synch
Break generation
Completion of Synch
Field measurement
Bus collision detection
There are four interrupt requests generated by the hardware LIN: Synch Break detection, Completion of Synch
Break generation, Completion of Synch Field measurement, and bus collision detection. These interrupts are
shared with timer RA.
Table 26.2 lists the Hardware LIN Interrupt Requests.
Interrupt Request
Interrupt Requests
Preliminary specification
Specifications in this manual are tentative and subject to change.
Hardware LIN Interrupt Requests
Nov 05, 2008
Status Flag
BCDCT
SBDCT
SFDCT
Generated when the RXD0 input and TXD0 output values
Generated when timer RA underflows after the “L” level
duration for the RXD0 input is measured, or when a “L” level
is input for a duration longer than the Synch Break period
during communication.
Generated when a “L” level output to TXD0 for the duration
set by timer RA is completed.
Generated when measurement for 6 bits of the Lynch Field
by timer RA is completed.
are different at data latch timing while UART0 is enabled for
transmission.
Interrupt Source
26. Hardware LIN