R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 200
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 170 of 583
15.2.8
Note:
1.
NMIF Bit (Non-Maskable Interrupt Generation Bit)
After Reset
Bit
b0
b1
b2
b3
b4
b5
b6
b7
Address 0080h
This bit is set to 0 when the read result is 1 and 0 is written to the same bit. This bit remains
unchanged even if the read result is 0 and 0 is written to the same bit. This bit remains unchanged if
1 is written to it.
The DTCTL register controls DTC activation when a non-maskable interrupt (an interrupt by the watchdog
timer, oscillation stop detection, voltage monitor 1, or voltage monitor 2) is generated.
The NMIF bit is set to 1 when a watchdog timer interrupt, an oscillation stop detection interrupt, a voltage
monitor 1 interrupt, or a voltage monitor 2 interrupt is generated.
When the NMIF bit is 1, the DTC is not activated even if the interrupt which enables DTC activation is
generated. If the NMIF bit is changed to 1 during DTC transfer, the transfer is continued until it is completed.
When an interrupt source is the watchdog timer, wait for the following cycles before writing 0 to the NMIF bit:
If the WDTC7 bit in the WDTC register is set to 0 (divide-by-16 using the prescaler), wait for 16 cycles of the
CPU clock after the interrupt source is generated.
If the WDTC7 bit is set to 1 (divide-by-128 using the prescaler), wait for 128 cycles of the CPU clock after the
interrupt source is generated.
When an interrupt source is oscillation stop detection, set to the OCD1 bit in the OCD register to 0 (oscillation
stop detection interrupt disabled) before writing 0 to the NMIF bit.
Symbol
Symbol
Bit
NMIF
DTC Activation Control Register (DTCTL)
—
—
—
—
—
—
—
Preliminary specification
Specifications in this manual are tentative and subject to change.
b7
—
0
Reserved bit
Non-maskable interrupt generation
bit
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
(1)
b6
—
0
Nov 05, 2008
Bit Name
b5
—
0
b4
—
0
Set to 0.
0: Non-maskable interrupts not generated
1: Non-maskable interrupts generated
b3
—
0
b2
—
0
Function
NMIF
b1
0
b0
—
0
15. DTC
R/W
R/W
R/W
—
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