R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 269
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 239 of 583
Figure 19.4
The above applies under the following conditions:
• The BFC bit in the TRCMR register is set to 1 (the TRCGRC register functions as the buffer register for the TRCGRA register).
• Bits IOA2 to IOA0 in the TRCIOR0 register are set to 001b (“L” output at compare match).
Make the following settings in timer mode.
• To use the TRCGRC register as the buffer register for the TRCGRA register:
• To use the TRCGRD register as the buffer register for the TRCGRB register:
The output compare function, PWM mode, or PWM2 mode, and the TRCGRC or TRCGRD register is
functioning as a buffer register, the IMFC bit or IMFD bit in the TRCSR register is set to 1 when a compare
match with the TRC register occurs.
The input capture function and the TRCGRC register or TRCGRD register is functioning as a buffer register,
the IMFC bit or IMFD bit in the TRCSR register is set to 1 at the input edge of a signal input to the TRCIOC pin
or TRCIOD pin.
TRCGRC register
TRCGRA register
Set the IOC2 bit in the TRCIOR1 register to the same value as the IOA2 bit in the TRCIOR0 register.
Set the IOD2 bit in the TRCIOR1 register to the same value as the IOB2 bit in the TRCIOR0 register.
TRCIOA output
TRC register
TRCGRC
(buffer)
Preliminary specification
Specifications in this manual are tentative and subject to change.
register
Buffer Operation for Output Compare Function
Nov 05, 2008
m-1
Compare match signal
TRCGRA
m
register
m
n
Comparator
Transfer
m+1
n
TRC
19. Timer RC
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