R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 523

• Manufacturer Part Number: R5F21324ANSP#U1
• Description: MCU 1KB FLASH 16K ROM 20-LSSOP
• Manufacturer: Renesas Electronics America
• Series: R8C/3x/32Ar

Specifications of R5F21324ANSP#U1

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, PWM, Voltage Detect, WDT
• Number Of I /o: 15
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-LSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 493 of 583
BYSAEI Bit (Flash Access Error Interrupt Request Flag)
LBDATA Bit (LBDATA Monitor Flag)
FST4 Bit (Program Error Flag)
FST5 Bit (Erase Error/Blank Check Error Flag)
FST6 Bit (Erase Suspend Status Flag)
FST7 Bit (Ready/Busy Status Flag)
[Conditions for setting to 0]
(1) Set to 0 by an interrupt handling program.
(2) Execute the status clear instruction.
[Conditions for setting to 1]
The BYSAEI bit is set to 1 (flash access error interrupt request) when the BSYAEIE bit in the FMR0 register is
set to 1 (flash access error interrupt enabled) and the block during auto-programming/auto-erasure is accessed.
This bit is also set to 1 if an erase or program error occurs when the CMDERIE bit in the FMR0 register is set to
1 (erase/write error interrupt enabled).
During interrupt handling, set the BSYAEI bit to 0 (no flash access error interrupt request).
(1) Read or write the area that is being erased/written when the BSYAEIE bit in the FRMR0 register is set to 1
(2) If a command sequence error, erase error, blank check error, or program error occurs when the CMDERIE
This is a read-only bit indicating the lock bit status. To confirm the lock bit status, execute the read lock bit
status command and read the LBDATA bit after the FST7 bit is set to 1 (ready).
The condition for updating this bit is when the program, erase, read lock bit status commands are generated.
When the read lock bit status command is input, the FST7 bit is set to 0 (busy). At the time when the FST7 bit
is set to 1 (ready), the lock bit status is stored in the LBDATA bit. The data in the LBDATA bit is retained until
the next command is input.
This is a read-only bit indicating the auto-programming status. The bit is set to 1 if a program error occurs;
otherwise, it is set to 0. For details, refer to the description in 30.4.12 Full Status Check.
This is a read-only bit indicating the status of auto-programming or the block blank check command. The bit is
set to 1 if an erase error or blank check error occurs; otherwise, it is set to 0. Refer to 30.4.12 Full Status Check
for details.
This is a read-only bit indicating the suspend status. The bit is set to 1 when an erase-suspend request is
acknowledged and a suspend status is entered; otherwise, it is set to 0.
This is a read-only bit indicating the operating status of the flash memory. The bit is set to 0 during program and
erase operations; otherwise, it is set to 1.
and while the flash memory is busy.
Or, read the data flash area while erasing/writing to the program ROM area. (Note that the read value is
undefined in both cases. Writing has no effect.)
bit in the FMR0 register is set to 1 (erase/write error interrupt enabled).
Preliminary specification
Specifications in this manual are tentative and subject to change.
Nov 05, 2008
30. Flash Memory