R5F21324ANSP#U1 Renesas Electronics America, R5F21324ANSP#U1 Datasheet - Page 161
R5F21324ANSP#U1
Manufacturer Part Number
R5F21324ANSP#U1
Description
MCU 1KB FLASH 16K ROM 20-LSSOP
Manufacturer
Renesas Electronics America
Series
R8C/3x/32Ar
Datasheet
1.R5F21322ANSPU1.pdf
(629 pages)
Specifications of R5F21324ANSP#U1
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, PWM, Voltage Detect, WDT
Number Of I /o
15
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-LSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Under development
R8C/32A Group
REJ09B0458-0020 Rev.0.20
Page 131 of 583
Figure 11.4
11.3.5
11.3.6
Table 11.5
Watchdog timer, oscillation stop detection, voltage monitor 1/comparator A1,
voltage monitor 2/comparator A2, address break
Software, address match, single-step
Figure 11.4 shows the Interrupt Response Time. The interrupt response time is the period from when an
interrupt request is generated until the first instruction in the interrupt routine is executed. The interrupt
response time includes the period from when an interrupt request is generated until the currently executing
instruction is completed (refer to (a) in Figure 11.4) and the period required for executing the interrupt sequence
(20 cycles, refer to (b) in Figure 11.4).
When a maskable interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt
is set in the IPL.
When a software interrupt or special interrupt request is acknowledged, the level listed in Table 11.5 is set in
the IPL.
Table 11.5 lists the IPL Value When Software or Special Interrupt is Acknowledged.
Interrupt request generation
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
IPL Value When Software or Special Interrupt is Acknowledged
Preliminary specification
Specifications in this manual are tentative and subject to change.
Interrupt Response Time
Interrupt Source without Interrupt Priority Level
(a) The period from when an interrupt request is generated until the currently executing instruction is completed.
(b) 21 cycles for address match and single-step interrupts.
The length of time varies depending on the instruction being executed. The DIVX instruction requires
the longest time, 30 cycles (no wait states if the divisor is a register).
Instruction
(a)
Nov 05, 2008
Interrupt response time
Interrupt request acknowledgement
Interrupt sequence
20 cycles (b)
interrupt routine
Instruction in
Time
Value Set in IPL
Not changed
7
11. Interrupts
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