ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 55

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
Note:
1
2
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
TLI, reset and TRAP can be considered as having the highest software priority in the
decision process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
●
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced
according to the flowchart in
●
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority.
See the reset chapter for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
●
●
The clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being
serviced) will therefore be lost if the clear sequence is executed.
TRAP (non-maskable software interrupt)
reset
External interrupts
External interrupts allow the processor to exit from Halt low-power mode. External
interrupt sensitivity is software selectable through the External Interrupt Control register
(EICR).
External interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to exit from Halt mode except those
mentioned in the “Interrupt Mapping” table. A peripheral interrupt occurs when a
specific flag is set in the peripheral status registers and if the corresponding enable bit
is set in the peripheral control register.
The general sequence for clearing an interrupt is based on an access to the status
register followed by a read or write to an associated register.
Figure
20). After stacking the PC, X, A and CC registers (except for reset), the
Figure
Doc ID 12321 Rev 5
20.
Interrupts
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