ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 171

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
Use the following procedure when the ST7 writes a word in RAM:
1.
2.
3.
4.
5.
6.
Word mode does not guarantee byte-pair coherency of words WRITTEN by the I2C master
in RAM and read by the ST7. Byte pair coherency in this case must be handled by software.
Figure 73. 16-bit word write operation flowchart
Byte-Pair Coherency ensured by setting Word Mode
RAM start address depends on slave address
Word mode is disabled by hardware after the word update is performed. It must be
enabled before each word update by CPU.
Disable interrupts
Enable Word mode by setting the B/W and BusyW bits in the I2C3SCR2 register.
BusyW bit is set to 1 when modifying any bits in Control Register 2. Writing a 1 to this
bit does not actually modify BusyW but prevents accidental clearing of the bit.
Write Byte 1 in an even address in RAM. The byte is not actually written in RAM but in
a shadow register. This address must be within the I2C RAM buffer of slave addresses
1, 2 or 3.
Write Byte 2 in the next higher address in RAM. This byte is actually written in RAM.
During the next cycle, the shadow register content is written in the lower address. The
DMA request is disabled during this cycle.
Byte mode resumes automatically after writing byte 2 and DMA is re-enabled.
Enable interrupts
Repeat
Sends write address
Sends 1 byte of data
STOP condition
Sends address
and write bit
HOST
Doc ID 12321 Rev 5
Decodes I2C3SNS address
Resets I2C3SNS write flag
Updates current address-
register + I2C3S disabled
Sets BUSYW in control -
completes word write
Writes one byte to RAM
Enables I2C3SNS
Issues DMA request
Delays while CPU
issues interrupt
decodes R/W bit
ST7 I2C3SNS
sets write flag
register
Word mode?
Y
N
Reads I2C3SNS status register
1 Cycle
Services I2C3SNS interrupt
max
Updates control register
Resumes execution
Normal execution
Halts execution
ST7 CPU
On-chip peripherals
1 Cycle
max
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