ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 244

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

Known limitations
16.6
16.6.1
16.6.2
16.6.3
16.7
16.7.1
16.7.2
16.7.3
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Random read operations not supported with the standard I²C
Description
The standard I²C peripheral is not fully compliant with random read capabilities (only the
I2C3SNS interface supports these capabilities). If the master sends a Restart condition, a
bus error is generated on the ST7 device in slave mode.
Occurrence
The occurrence of the problem is random.
Workaround
The Restart condition is not allowed. The master must not send a Restart condition. It must
send a Stop condition before a second Start (each Start has to be preceded by a Stop).
Programming of EEPROM data
Description
In user mode, when programming EEPROM data memory, the read access to the program
memory between E000h and FFFFh can be corrupted.
Impact on application
The EEPROM programming routine must be located outside this program memory area.
Any access to the interrupt vector table can result in an unexpected code being executed, so
the interrupts must be masked.
Workaround
The sequence to program the EEPROM data (refer to
executed within C000h-DFFFh area or from the RAM. It is as follows:
set E2LAT bit
write up to 32 bytes in E2PROM area
SIM ; to disable the interrupts
set E2PGM bit
wait for E2PGM=0
RIM ; to enable the interrupts
return to the program memory
Doc ID 12321 Rev 5
Section 5.3 on page
ST72344xx ST72345xx
31) must be