ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 126

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

On-chip peripherals
Note:
Note:
Note:
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Bit 4 = MSTR Master Mode
Bit 3 = CPOL Clock Polarity
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial clock frequency
These 2 bits have no effect in slave mode.
Table 54.
SPI control/status register (SPICSR)
Reset value: 0000 0000 (00h)
7
SPIF
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
SPI master mode SCK frequency
WCOL
Serial clock
f
f
f
f
CPU
f
f
CPU
CPU
CPU
Read-only
CPU
CPU
/128
/16
/32
/64
/4
/8
Master mode fault (MODF) on page
OVR
Doc ID 12321 Rev 5
MODF
Reserved
SPR2
1
0
1
0
-
121).
SOD
SPR1
0
1
ST72344xx ST72345xx
Read/Write
SSM
0
SPR0
0
1
0
1
SSI