ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 33

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
5.4
5.4.1
5.4.2
5.4.3
5.5
Figure 9.
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
Power saving modes
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active Halt mode.The data EEPROM will
immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
Active-halt mode
Refer to Wait mode.
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
Access error handling
If a read access occurs while E2LAT = 1, then the data bus will not be driven.
If a write access occurs while E2LAT = 0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
E2PGM bit
E2LAT bit
definition
Row
Data EEPROM write operation
Byte 1 Byte 2
⇓ Row / Byte ⇒ 0 1 2 3
Set by USER application
Writing data latches
...
N
0
1
PHASE 1
Read operation impossible
Doc ID 12321 Rev 5
Byte 32
Waiting E2PGM and E2LAT to fall
Programming cycle
PHASE 2
...
30 31
Nx20h...Nx20h+1Fh
Physical address
Read operation possible
00h...1Fh
20h...3Fh
Cleared by hardware
Data EEPROM
33/247