ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 135

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

ST72344xx ST72345xx
Note:
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next byte
in the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9
bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
Break character
Idle character
During a SCI reception, data shifts in least significant bit first through the RDI pin. In
this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and
the received shift register (see
Procedure:
–
–
–
When a character is received:
–
–
–
Clearing the RDRF bit is performed by the following software sequence done by:
a)
b)
The RDRF bit must be cleared before the end of the reception of the next character to
avoid an overrun error.
When a break character is received, the SCI handles it as a framing error.
When an idle frame is detected, there is the same procedure as a data received
character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR
register.
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
Set the RE bit, this enables the receiver which begins searching for a start bit.
The RDRF bit is set. It indicates that the content of the shift register is transferred
to the RDR.
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR
register.
The error flags can be set if a frame error, noise or an overrun error has been
detected during reception.
An access to the SCISR register
A read to the SCIDR register.
Doc ID 12321 Rev 5
Figure
63).
On-chip peripherals
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