ST72F344K4T6 STMicroelectronics, ST72F344K4T6 Datasheet - Page 174

• Manufacturer Part Number: ST72F344K4T6
• Description: MCU 8BIT 16KB FLASH MEM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F344K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST72F34X-SK/RAIS, ST7MDT40-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5611

On-chip peripherals
Note:
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When the memory address limit is reached the current address will roll over and the
sequential read will continue till the addressing master sends a stop condition. Refer to
Figure 81
Combined format
If a master wants to continue communication either with another slave or by changing the
direction of transfer then the master would generate a restart and provide a different slave
address or the same slave address with the R/W bit reversed. Refer to
Rollover handling
The RAM buffer of each slave is divided into pages whose length is defined according to
PL1:0 bits in I2C3SCR1. Rollover takes place in these pages as described below.
In the case of Page Write, if the number of data bytes transmitted is more than the page
length, the current address will roll over to the first byte of the current page and the previous
data will be overwritten. This page size is configured using PL[1:0] bit in the I2C3SCR1
register.
In case of Sequential Read, if the current address register value reaches the memory
address limit the address will roll over to the first address of the reserved area for the
respective slave.
There is no status flag to indicate the roll over.
The reserved areas for slaves 1 and 2 have a limit of 256 bytes. The area for slave 3 is 128
bytes. The MSB of the address is hardwired, the addressing master therefore needs to send
only an 8 bit address.
The page boundaries are defined based on page size configuration using PL[1:0] bit in the
I2C3SCR1 register. If an 8-byte page size is selected, the upper 5 bits of the RAM address
are fixed and the lower 3 bits are incremented. For example, if the page write starts at
register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x08,
0x09, 0x0A, 0x0B. If a 16-byte page size is selected, the upper 4 bits of the RAM address
are fixed and the lower 4 bits are incremented. For example if the page write starts at
register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x00,
0x01, etc.
Error conditions
●
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
BERR bit is set by hardware with an interrupt if ITER is set. During a stop condition, the
interface discards the data, releases the lines and waits for another Start condition.
However, a BERR on a Start condition will result in the interface discarding the data
and waiting for the next slave address on the bus.
NACK: Detection of a non-acknowledge bit not followed by a Stop condition. In this
case, NACK bit is set by hardware with an interrupt if ITER is set.
Doc ID 12321 Rev 5
ST72344xx ST72345xx
Figure
82.