MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 79

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.3 Integer Data Formats
Table 2-4 lists the integer operand data formats. Integer operands can reside in registers,
memory, or instructions. The operand size for each instruction is either explicitly encoded
in the instruction or implicitly defined by the instruction operation.
2.4 Organization of Data in Registers
The following sections describe data organization within the data, address, and control
registers.
2.4.1 Organization of Integer Data Formats in Registers
Figure 2-7 shows the integer format for data registers. Each integer data register is 32 bits
wide. Byte and word operands occupy the lower 8- and 16-bit portions of integer data
registers, respectively. Longword operands occupy the entire 32 bits of integer data
registers. A data register that is either a source or destination operand only uses or changes
the appropriate lower 8 or 16 bits in byte or word operations, respectively. The remaining
high-order portion does not change. The least significant bit (lsb) of all integer sizes is zero,
the most-significant bit (msb) of a longword integer is 31, the msb of a word integer is 15,
and the msb of a byte integer is 7.
The instruction set encodings do not allow the use of address registers for byte-sized
operands. When an address register is a source operand, either the low-order word or the
entire longword operand is used, depending on the operation size. Word-length source
msb
msb
31
31
31
31
Figure 2-7. Organization of Integer Data Formats in Data Registers
30
Not used
Not used
Table 2-4. Integer Data Formats
Bit
Byte integer
Word integer
Longword integer
Longword
Operand Data Format
Chapter 2. ColdFire Core
msb
15
msb Low order byte
7
Lower order word
1
16 bits
32 bits
8 bits
Size
lsb
lsb
lsb
lsb
1 bit
0
0
0
0
Bit (0 ≤ bit number ≤ 31)
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Integer Data Formats
2-13