MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 410

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Overview
17-4
Address configuration
BE[3:0] configuration
Divide control PCLK to
CLKIN
Chip selects[7:0]
Byte enable[3:0]/
Byte write enable[3:0]
Output enable
Row address strobe
Column address strobe
DRAM write
Synchronous column
address strobe
Synchronous row
address strobe
Synchronous clock
enable
Synchronous edge
select
DMA request
DMA acknowledge
Receive data
Transmit data
Request-to-send
Clear-to-send
Timer input
Signal Name
2
2
Table 17-1. MCF5407 Signal Index (Continued)
ADDR_CONFIG
BE_CONFIG
DIVIDE[2:0]
CS[7:0]
BE[3:0]/
BWE[3:0]
OE
RAS[1:0]
CAS[3:0]
DRAMW
SCAS
SRAS
SCKE
EDGESEL
DREQ[1:0]
DACK[1:0]
RxD[1:0]
TxD[1:0]
RTS[1:0]
CTS[1:0]
TIN[1:0]
Abbreviation
Section 17.8, “DMA Controller Module Signals”
Section 17.6, “Chip-Select Module Signals”
Section 17.7, “DRAM Controller Signals”
Section 17.10, “Timer Module Signals”
Section 17.9, “Serial Module Signals”
MCF5407 User’s Manual
Programs parallel I/O ports
Programs byte enable pins
Selects CLKIN/PCLK ratio
Enables peripherals at programmed
addresses; CS0 provides boot ROM
selection.
BE[3:0] select bytes in memory.
Programmed at reset for CS0
Output enable for chip select read
cycles
DRAM row address strobe
DRAM column address strobe
Asserted for DRAM write; negated
for DRAM read
SDRAM column address strobe
SDRAM row address strobe
Clock enable for external SDRAM
Timing select for external SDRAM
External DMA transfer request;
multiplexed with PP[6:5]
Indicates DMA transfer terminated;
multiplexed with TM[1:0]/PP[3:2]
Receive serial data input for UART
Transmit serial data output for UART
UART asserts when ready to
receive data query.
Signals UART that data can be sent
to peripheral
Clock input to timer or trigger to
timer value capture logic
Function
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Parallel
Reset
High
High
High
High
High
High
High
High
High
High
Low
port
—
—
—
—
—
—
—
—
User cfg 17-15
User cfg 17-15
User cfg 17-15
User cfg 17-17
Pull-Up Page
17-15
17-15
17-16
17-16
17-16
17-16
17-16
17-16
17-17
17-17
17-17
17-17
17-17
17-18
17-18
17-19
17-18
17-19
17-19
17-19
17-19