MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 203

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

processing begins. After the standard 8-byte exception stack is created, the processor
fetches a unique exception vector from the vector table. Table 5-26 describes the two
unique entries that distinguish PC breakpoints from other trigger events.
In the case of a two-level trigger, the last breakpoint event determines the exception vector;
however, if the second-level trigger is PC || Address {&& Data} (as shown in the last
condition in the code example in Section 5.4.9, “Resulting Set of Possible Trigger
Combinations”), the vector taken is determined by the first condition that occurs after the
first-level trigger—vector 13 if PC occurs first or vector 12 if Address {&& Data} occurs
first. If both occur simultaneously, the non-PC-breakpoint debug interrupt is taken (vector
number 12).
Execution continues at the instruction address in the vector corresponding to the breakpoint
triggered. The debug interrupt handler can use supervisor instructions to save the necessary
context such as the state of all program-visible registers into a reserved memory area.
During a debug interrupt service routine, all normal interrupt requests are evaluated and
sampled once per instruction. If any exception occurs, the processor responds as follows:
Fault status encodings are listed in Table 2-21. Implementation of this debug interrupt
handling fully supports the servicing of a number of normal interrupt requests during a
debug interrupt service routine. The emulator mode state bit is essentially changed to be a
program-visible value, stored into memory during exception stack frame creation, and
loaded from memory by the RTE instruction.
When debug interrupt operations complete, the RTE instruction executes and the processor
exits emulator mode. After the debug interrupt handler completes execution, the external
Vector Number
1. It saves a copy of the current value of the emulator mode state bit and then exits
2. Bit 1 of the fault status field (FS1) in the next exception stack frame is set to indicate
3. It passed control to the appropriate exception handler.
4. It executes an RTE instruction when the exception handler finishes. During the
12
13
emulator mode by clearing the actual state.
the processor was in emulator mode when the interrupt occurred. This corresponds
to bit 17 of the longword at the top of the system stack. See Section 2.8.1,
“Exception Stack Frame Definition.”
processing of the RTE, FS1 is reloaded from the system stack. If this bit is set, the
processor sets the emulator mode state and resumes execution of the original debug
interrupt service routine. This is signaled externally by the generation of the PST
value that originally identified the debug interrupt exception, that is, PST = 0xD.
Vector Offset (Hex)
0x030
0x034
Table 5-26. Exception Vector Assignments
Chapter 5. Debug Support
Stacked Program Counter
Next
Next
Non-PC-breakpoint debug interrupt
PC-breakpoint debug interrupt
Real-Time Debug Support
Assignment
5-47