MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet
MCF5407AI220
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MCF5407AI220 Summary of contents
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MCF5407 ColdFire Integrated Microprocessor User’s Manual MCF5407UM/D Rev. 0.1, 11/2001 ® ...
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ColdFire is a registered trademark and DigitalDNA is a trademark of Motorola, Inc registered trademark of Philips Semiconductors Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no ...
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Hardware Multiply/Accumulate (MAC) Unit Part II: System Integration Module (SIM) Synchronous/Asynchronous DRAM Controller Module Parallel Port (General-Purpose I/O) IEEE 1149.1 Test Access Port (JTAG) Glossary of Terms and Abbreviations Part I: MCF5407 Processor Core ColdFire Core Local Memory Debug Support ...
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Overview 1 Part I: MCF5407 Processor Core Part I ColdFire Core 2 Hardware Multiply/Accumulate (MAC) Unit 3 Local Memory 4 Debug Support 5 Part II: System Integration Module (SIM) Part II SIM Overview 6 Phase-Locked Loop (PLL ...
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Paragraph Number 1.1 Features ............................................................................................................... 1-1 1.2 MCF5407 Features.............................................................................................. 1-4 1.2.1 Process ............................................................................................................ 1-7 1.3 ColdFire Module Description ............................................................................. 1-7 1.3.1 ColdFire Core ................................................................................................. 1-7 1.3.1.1 Instruction Fetch Pipeline (IFP).................................................................. 1-7 1.3.1.2 Operand Execution Pipeline (OEP) ............................................................ 1-8 1.3.1.3 MAC ...
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Paragraph Number 1.4.3 Supervisor Registers ..................................................................................... 1-16 1.4.4 Instruction Set ............................................................................................... 1-16 2.1 Features and Enhancements................................................................................ 2-1 2.1.1 Clock-Multiplied Microprocessor Core.......................................................... 2-2 2.1.2 Enhanced Pipelines ......................................................................................... 2-2 2.1.2.1 Instruction Fetch Pipeline (IFP).................................................................. 2-4 2.1.2.1.1 Branch Acceleration ............................................................................... 2-4 2.1.2.2 Operand ...
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Paragraph Number 2.6.2 Instruction Set Summary .............................................................................. 2-19 2.7 Execution Timings ............................................................................................ 2-23 2.7.1 MOVE Instruction Execution Timing .......................................................... 2-25 2.7.2 Execution Timings—One-Operand Instructions .......................................... 2-26 2.7.3 Execution Timings—Two-Operand Instructions.......................................... 2-27 2.7.4 Miscellaneous Instruction Execution Times................................................. 2-29 2.7.5 Branch Instruction ...
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Paragraph Number 4.9.2 Cache-Inhibited Accesses ............................................................................. 4-14 4.9.3 Cache Protocol.............................................................................................. 4-15 4.9.3.1 Read Miss ................................................................................................. 4-16 4.9.3.2 Write Miss (Data Cache Only) ................................................................. 4-16 4.9.3.3 Read Hit .................................................................................................... 4-16 4.9.3.4 Write Hit (Data Cache Only) .................................................................... 4-17 4.9.4 Cache Coherency ...
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Paragraph Number 5.4.9 Resulting Set of Possible Trigger Combinations.......................................... 5-21 5.5 Background Debug Mode (BDM) .................................................................... 5-22 5.5.1 CPU Halt....................................................................................................... 5-22 5.5.2 BDM Serial Interface.................................................................................... 5-24 5.5.2.1 Receive Packet Format ............................................................................. 5-25 5.5.2.2 Transmit Packet Format............................................................................ 5-26 5.5.3 BDM Command ...
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Paragraph Number 6.2.2 Module Base Address Register (MBAR) ....................................................... 6-4 6.2.3 Reset Status Register (RSR) ........................................................................... 6-5 6.2.4 Software Watchdog Timer.............................................................................. 6-6 6.2.5 System Protection Control Register (SYPCR) ............................................... 6-8 6.2.6 Software Watchdog Interrupt Vector Register (SWIVR)............................... 6-9 6.2.7 Software ...
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Paragraph Number 2 8.5 Address Register (IADR) ......................................................................... 8-6 2 8.5 Frequency Divider Register (IFDR)......................................................... 8-6 2 8.5 Control Register (I2CR) ........................................................................... 8-7 2 8.5 Status Register (I2SR).............................................................................. 8-8 2 8.5.5 I ...
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Paragraph Number 11.1 Overview........................................................................................................... 11-1 11.1.1 Definitions .................................................................................................... 11-2 11.1.2 Block Diagram and Major Components ....................................................... 11-2 11.2 DRAM Controller Operation ............................................................................ 11-3 11.2.1 DRAM Controller Registers ......................................................................... 11-3 11.3 Asynchronous Operation .................................................................................. 11-4 11.3.1 DRAM Controller Signals in Asynchronous ...
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Paragraph Number 12.1 Overview........................................................................................................... 12-1 12.1.1 DMA Module Features ................................................................................. 12-2 12.2 DMA Signal Description .................................................................................. 12-2 12.3 DMA Transfer Overview.................................................................................. 12-4 12.4 DMA Controller Module Programming Model................................................ 12-5 12.4.1 Source Address Registers (SAR0–SAR3) .................................................... 12-7 12.4.2 Destination Address Registers ...
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Paragraph Number 13.3.5 Timer Event Registers (TER0/TER1)........................................................... 13-5 13.4 Code Example................................................................................................... 13-6 13.5 Calculating Time-Out Values ........................................................................... 13-7 14.1 Overview........................................................................................................... 14-1 14.2 Serial Module Overview ................................................................................... 14-2 14.3 Register Descriptions ........................................................................................ 14-3 14.3.1 UART Mode Registers 1 (UMR1n).............................................................. 14-5 14.3.2 ...
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Paragraph Number 14.5.2.4.1 Receiver in Modem Mode (UART1).................................................. 14-31 14.5.2.5 FIFO Stack in UART0............................................................................ 14-32 14.5.2.6 FIFOs in UART1 .................................................................................... 14-33 14.5.3 Looping Modes ........................................................................................... 14-34 14.5.3.1 Automatic Echo Mode ............................................................................ 14-34 14.5.3.2 Local Loop-Back Mode .......................................................................... 14-34 14.5.3.3 Remote ...
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Paragraph Number 17.2.1.1 Address Bus (A[23:0]).............................................................................. 17-7 17.2.1.2 Address Bus (A[31:24]/PP[15:8]) ............................................................ 17-7 17.2.2 Data Bus (D[31:0]) ....................................................................................... 17-8 17.2.3 Read/Write (R/W)......................................................................................... 17-8 17.2.4 Size (SIZ[1:0]) .............................................................................................. 17-8 17.2.5 Transfer Start (TS) ........................................................................................ 17-9 17.2.6 Address Strobe (AS) ..................................................................................... 17-9 ...
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Paragraph Number 17.8.2 Transfer Modifier/DMA Acknowledge (TM[2:0]/DACK[1:0]) ................ 17-18 17.9 Serial Module Signals ..................................................................................... 17-18 17.9.1 Transmitter Serial Data Output (TxD)........................................................ 17-18 17.9.2 Receiver Serial Data Input (RxD)............................................................... 17-19 17.9.3 Clear to Send (CTS).................................................................................... 17-19 17.9.4 Request to Send (RTS) ...
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Paragraph Number 18.4.7.4 Transfers Using Mixed Port Sizes .......................................................... 18-15 18.5 Misaligned Operands ...................................................................................... 18-16 18.6 Bus Errors ....................................................................................................... 18-17 18.7 Interrupt Exceptions........................................................................................ 18-17 18.7.1 Level 7 Interrupts........................................................................................ 18-18 18.7.2 Interrupt-Acknowledge Cycle..................................................................... 18-19 18.8 Bus Arbitration................................................................................................ 18-20 18.8.1 Bus Arbitration ...
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Paragraph Number 20.9 Parallel Port (General-Purpose I/O) Timing Specifications ........................... 20-22 20.10 DMA Timing Specifications........................................................................... 20-23 20.11 IEEE 1149.1 (JTAG) AC Timing Specifications ........................................... 20-24 Migrating from the ColdFire MCF5307 to the MCF5407 A.1 Overview............................................................................................................ A-1 A.2 Instruction Set Additions ...
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Paragraph Number xx CONTENTS Title MCF5407 User’s Manual Page Number ...
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Figure Number 1-1 MCF5407 Block Diagram............................................................................................. 1-2 1-2 UART Module Block Diagram................................................................................... 1-10 1-3 PLL Module ................................................................................................................ 1-13 1-4 ColdFire MCF5407 Programming Model .................................................................. 1-15 2-1 ColdFire Enhanced Pipeline ......................................................................................... 2-3 2-2 ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-5 2-3 ColdFire ...
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Figure Number 5-7 Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)............................ 5-12 5-8 BDM Address Attribute Register (BAAR)................................................................. 5-13 5-9 Configuration/Status Register (CSR).......................................................................... 5-13 5-10 Data Breakpoint/Mask Registers (DBR/DBR1 and DBMR/DBMR1)....................... 5-16 5-11 Program Counter Breakpoint Registers (PBR, PBR1, PBR2, PBR3) ...
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Figure Number 6-4 MCF5407 Embedded System Recovery from Unterminated Access........................... 6-7 6-5 System Protection Control Register (SYPCR) ............................................................ 6-8 6-6 Software Watchdog Interrupt Vector Register (SWIVR)............................................ 6-9 6-7 Software Watchdog Service Register (SWSR)............................................................ 6-9 6-8 Pin Assignment Register (PAR) ................................................................................. ...
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Figure Number 11-10 Write Hit in Continuous Page Mode......................................................................... 11-15 11-11 EDO Read Operation (3-2-2-2) ................................................................................ 11-15 11-12 DRAM Access Delayed by Refresh ......................................................................... 11-16 11-13 MCF5407 SDRAM Interface.................................................................................... 11-18 11-14 Using EDGESEL to Change Signal Timing............................................................. 11-19 11-15 DRAM ...
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Figure Number 14-5 Modem Control Register (MODCTL) ........................................................................ 14-9 14-6 Tx FIFO Threshold Register (TXLVL) .................................................................... 14-10 14-7 UART Status Register (USRn) ................................................................................. 14-10 14-8 UART Clock-Select Register (UCSRn).................................................................... 14-12 14-9 Receive Samples Available Register (RSMP).......................................................... 14-13 14-10 Tx Space ...
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Figure Number 18-1 Signal Relationship to CLKIN for Non-DRAM Access............................................. 18-2 18-2 Connections for External Memory Port Sizes ............................................................ 18-4 18-3 Chip-Select Module Output Timing Diagram ............................................................ 18-4 18-4 Data Transfer State Transition Diagram ..................................................................... 18-6 18-5 Read Cycle Flowchart................................................................................................. ...
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Figure Number 20-5 PSTCLK Timing......................................................................................................... 20-6 20-6 AC Timings—Normal Read and Write Bus Cycles ................................................... 20-8 20-7 SDRAM Read Cycle with EDGESEL Tied to Buffered CLKIN ............................... 20-9 20-8 SDRAM Write Cycle with EDGESEL Tied to Buffered CLKIN ............................ 20-10 ...
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Figure Number xxviii ILLUSTRATIONS Title MCF5407 User’s Manual Page Number ...
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Table Number 1-1 User-Level Registers................................................................................................... 1-15 1-2 Supervisor-Level Registers......................................................................................... 1-16 2-1 CCR Field Descriptions ............................................................................................. 2-10 2-2 MOVEC Register Map ............................................................................................... 2-11 2-3 Status Field Descriptions ............................................................................................ 2-11 2-4 Integer Data Formats................................................................................................... 2-13 2-5 ColdFire Effective Addressing Modes........................................................................ 2-15 ...
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Table Number 4-10 Data Cache Line State Transitions (Current State Modified)..................................... 4-31 5-1 Debug Module Signals.................................................................................................. 5-2 5-2 PSTDDATA: Sequential Execution of Single-Cycle Instructions .............................. 5-3 5-3 PSTDDATA: Data Operand Captured.......................................................................... 5-4 5-4 Processor Status Encoding............................................................................................ 5-5 5-5 0xE Status ...
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Table Number 8-5 I2SR Field Descriptions................................................................................................ 8-9 9-1 Interrupt Controller Registers ....................................................................................... 9-2 9-2 Interrupt Control Registers ........................................................................................... 9-2 9-3 ICRn Field Descriptions ............................................................................................... 9-3 9-4 Interrupt Priority Scheme.............................................................................................. 9-4 9-5 AVR Field Descriptions................................................................................................ 9-6 9-6 Autovector Register Bit Assignments........................................................................... ...
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Table Number 11-25 MCF5407 to SDRAM Interface (16-Bit Port, 13-Column-Address Lines) ............. 11-26 11-26 MCF5407 to SDRAM Interface (32-Bit Port, 8-Column Address Lines)................ 11-26 11-27 MCF5407 to SDRAM Interface (32-Bit Port, 9-Column Address Lines)................ 11-26 11-28 MCF5407 to SDRAM Interface ...
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Table Number 15-3 Relationship between PADAT Register and Parallel Port Pin (PP) ........................... 15-3 16-1 Pins 1–52 (Left, Top-to-Bottom) ................................................................................ 16-1 16-2 Pins 53–104 (Bottom, Left-to-Right).......................................................................... 16-3 16-3 Pins 105–156 (Right, Bottom-to-Top)........................................................................ 16-5 16-4 Pins 157–208 (Top, Right-to-Left) ............................................................................. 16-6 ...
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Table Number 20-7 Output AC Timing Specification ................................................................................ 20-6 20-8 Reset Timing Specification....................................................................................... 20-15 20-9 Debug AC Timing Specification .............................................................................. 20-16 20-10 Timer Module AC Timing Specification.................................................................. 20- Input Timing Specifications between SCL and SDA......................................... 20-18 20-11 I ...
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About This Book The primary objective of this user’s manual is to define the functionality of the MCF5407 processors for use by software and hardware developers. The information in this book is subject to change without notice, as described in ...
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Organization — Chapter 3, “Hardware Multiply/Accumulate (MAC) Unit,” describes the MCF5407 multiply/accumulate unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). — Chapter 4, “Local Memory.” This chapter describes ...
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SIM. It begins with a general description and brief glossary, and includes a description of signals involved in DRAM operations. The remainder of the chapter is divided between descriptions of asynchronous and synchronous operations. • Part ...
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Suggested Reading — Chapter 20, “Electrical Specifications,” describes AC and DC electrical specifications and thermal characteristics for the MCF5407. Because additional speeds may have become available since the publication of this book, consult Motorola’s ColdFire web page, http://www.motorola.com/coldfire, to confirm ...
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Using Microprocessors and Microcomputers: The Motorola Family, William C. Wray, Ross Bannatyne, Joseph D. Greenfield Additional literature on ColdFire implementations is being released as new processors become available. For a current list of ColdFire documentation, refer to the World ...
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Acronyms and Abbreviations Table i. Acronyms and Abbreviated Terms (Continued) Term BDM Background debug mode BIST Built-in self test BSDL Boundary-scan description language CODEC Code/decode DAC Digital-to-analog conversion DMA Direct memory access DSP Digital signal processing EA Effective address EDO ...
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Table i. Acronyms and Abbreviated Terms (Continued) Term POR Power-on reset PQFP Plastic quad flat pack RISC Reduced instruction set computing Rx Receive SIM System integration module SOF Start of frame TAP Test access port TTL Transistor-to-transistor logic Tx Transmit ...
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Terminology and Notational Conventions Table ii Notational Conventions (Continued) Instruction ACC MAC accumulator register CCR Condition code register (lower byte of SR) MACSR MAC status register MASK MAC mask register PC Program counter SR Status register PSTDDATA Processor status/debug data ...
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Table ii Notational Conventions (Continued) Instruction / Arithmetic division ~ Invert; operand is logically complemented & Logical AND | Logical OR ^ Logical exclusive OR << Shift left (example: D0 << shift D0 left 3 bits) >> Shift ...
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Terminology and Notational Conventions xliv MCF5407 User’s Manual ...
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Chapter 1 Overview This chapter is an overview of the MCF5407 ColdFire descriptions of the modules and features incorporated in the MCF5407, focusing in particular on new features defined by the Version 4 (V4) programming model, such as the Harvard ...
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Features JTAG Debug Module ÷2 PSTCLK CLKIN Local Memory (to on-chip Instruction Bus peripherals) CLKIN PCLK PLL X n RSTI RSTO SYSTEM INTEGRATION MODULE (SIM) PLL Control System Control PLL RSR SWIVR SYPCR SWSR DRAM Controller Chip-Select Module DRAM Control ...
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Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated using advanced process technologies. The MCF5407 extends the legacy of Motorola’s 68K family by providing a compatible path for 68K and ColdFire ...
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MCF5407 Features 1.2 MCF5407 Features The following list summarizes MCF5407 features: • ColdFire processor core — Variable-length RISC, clock-multiplied Version 4 microprocessor core — Implementation of Revision B of the ColdFire instruction set architecture (ISA), which leverages the 68K programming ...
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Two, 2-Kbyte SRAMs — Programmable location anywhere within 4-Gbyte linear address space — Higher core-frequency operation — Pipelined, single-cycle access to critical code or data — Each block mappable to either the instruction or data operand bus • DMA ...
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MCF5407 Features 2 • module — Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads — Fully compatible with industry-standard I — Master or slave modes support multiple masters — Automatic interrupt generation with programmable level ...
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Process The MCF5407 is manufactured in a 0.22-µ CMOS process with quad-layer-metal routing technology. This process combines the high performance and low power needed for embedded system applications. Inputs are 3.3-V tolerant; outputs are CMOS or open-drain CMOS with ...
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ColdFire Module Description 1.3.1.2 Operand Execution Pipeline (OEP) The prefetched instruction stream is gated from the FIFO buffer into the five-stage OEP. The OEP consists of two, traditional two-stage RISC compute engines with a register file access feeding an arithmetic/logic ...
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Instruction Cache/8-Kbyte Data Cache The MCF5407 Harvard architecture includes a 16-Kbyte instruction cache and an 8-Kbyte data cache. These four-way, set-associative caches provide pipelined, single-cycle access on cached instructions and operands. As with all ColdFire caches, the cache ...
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ColdFire Module Description 1.3.5 UART Modules The MCF5407 contains two UARTs, which function independently. One UART has been enhanced to provide synchronous operation and a CODEC interface for soft modem support. Either UART can be clocked by the system bus ...
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UART connections. The programmable UARTs can interrupt the CPU on various normal or error-condition events. 1.3.6 Timer Module The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer ...
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ColdFire Module Description or 32-bit ports. The base address, access permissions, and internal bus transfer terminations are programmable with configuration registers for each chip select. CS0 also provides global chip select functionality of boot ROM upon reset for initializing the ...
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To support program trace, the Version 4 debug module has combined the processor status and debug data outputs into a single 8-bit bus (PSTDDATA[7:0]). This bus and the PSTCLK output provide execution status, captured operand data, and branch target addresses ...
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Programming Model, Addressing Modes, and Instruction Set • User mode—When the processor is in user mode (SR[S] = 0), only a subset of registers can be accessed, and privileged instructions cannot be executed. Typically, most application processing occurs in user ...
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Programming Model Figure 1-4 shows the MCF5407 programming model Figure 1-4. ColdFire MCF5407 Programming Model 1.4.2 User Registers The user programming model is shown in Figure 1-4 and summarized in Table 1-1. Register Data registers ...
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Programming Model, Addressing Modes, and Instruction Set Table 1-1. User-Level Registers (Continued) Register Program counter Contains the address of the instruction currently being executed by the MCF5407 processor (PC) Condition code The CCR is the lower byte of the SR. ...
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For two-operand instructions, the first operand is generally the source operand and the second is the destination. Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports most of the ...
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Programming Model, Addressing Modes, and Instruction Set 1-18 MCF5407 User’s Manual ...
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Intended Audience Part I is intended for system designers who need a general understanding of the functionality supported by the MCF5407. It also describes the operation of the MCF5407 ColdFire core and its multiply/accumulate (MAC) execution unit. It describes the ...
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Chapter 5, “Debug Support,” describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses earlier revisions. Suggested Reading The following literature may be helpful with respect to the topics in ...
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Table I-i. Acronyms and Abbreviated Terms (Continued) Term LRU Least recently used LSB Least-significant byte lsb Least-significant bit MAC Multiple accumulate unit MBAR Memory base address register MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand ...
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I-xxii MCF5407 User’s Manual ...
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Chapter 2 ColdFire Core This chapter provides an overview of the microprocessor core of the MCF5407. The chapter begins with a description of enhancements from the Version 3 (V3) ColdFire core, and then fully describes the V4 programming model as ...
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Features and Enhancements • Vector base register to relocate exception-vector table • Optimized for high-level language constructs 2.1.1 Clock-Multiplied Microprocessor Core The MCF5407 incorporates a clock-multiplying phase-locked loop (PLL). Increasing the internal speed of the core also allows higher performance ...
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Write data available (DA) makes data available for operand write operations only. — Store data (ST) updates memory element for operand write operations only. Instruction Fetch Pipeline IAG Branch IC1 Cache IC2 Branch IED Accel. IB Operand Execution Pipeline ...
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Features and Enhancements 2.1.2.1 Instruction Fetch Pipeline (IFP) Because the fetch and execution pipelines are decoupled by a ten-instruction FIFO buffer, the IFP can prefetch instructions before the OEP needs them, minimizing stalls. 2.1.2.1.1 Branch Acceleration To maximize the performance ...
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Instruction folding involving MOVE instructions allows two instructions to be issued in one cycle. The resulting microarchitecture approaches full superscalar performance at a much lower silicon cost. 2.1.2.2.1 Illegal Opcode Handling To aid in conversion from M68000 code, every ...
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Features and Enhancements 2.1.2.2.3 Hardware Divide Unit The hardware divide unit performs the following integer division operations: • 32-bit operand/16-bit operand producing a 16-bit quotient and a 16-bit remainder • 32-bit operand/32-bit operand producing a 32-bit quotient • 32-bit operand/32-bit ...
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These registers can be accessed through the dedicated debug serial communication channel, or from the processor’s supervisor programming model, using the WDEBUG instruction. The MCF5407’s new interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be ...
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Programming Model Figure 2-3. ColdFire Programming Model 2.2.1 User Programming Model As Figure 2-3 shows, the user programming model consists of the following registers: • 16 general-purpose 32-bit registers, D0–D7 and A0–A7 • 32-bit program counter ...
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Address Registers (A0–A6) The address registers (A0–A6) can be used as software stack pointers, index registers, or base address registers and may be used for word and longword operations. 2.2.1.3 Stack Pointer (A7, SP) The processor core supports a ...
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Programming Model Table 2-1. CCR Field Descriptions Bits Name 7–5 — Reserved, should be cleared Extend condition code bit. Assigned the value of the carry bit for arithmetic operations; otherwise not affected or set to a specified result. ...
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Table 2-2. MOVEC Register Map Rc[11–0] 0x002 0x004 0x005 0x006 0x007 0x801 0xC04 0xC05 0xC0F 2.2.2.1 Status Register (SR) The SR stores the processor status, the interrupt priority mask, and other control bits. Supervisor software can read or write the ...
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Programming Model 2.2.2.2 Vector Base Register (VBR) The VBR holds the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. VBR[19–0] ...
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Integer Data Formats Table 2-4 lists the integer operand data formats. Integer operands can reside in registers, memory, or instructions. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction ...
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Organization of Data in Registers operands are sign-extended to 32 bits and then used in the operation with anaddress register destination. When an address register is a destination, the entire register is affected, regardless of the operation size. Figure 2-8 ...
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Addressing Mode Summary Addressing modes are categorized by how they are used. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands. Alterable addressing modes refer to alterable (writable) data operands. Control addressing modes refer ...
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Instruction Set Summary Table 2-6. Notational Conventions Instruction cc Logical condition (example: NE for not equal) An Any address register n (example address register 3) Ay,Ax Source and destination address registers, respectively Dn Any data register n (example: ...
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Table 2-6. Notational Conventions (Continued) Instruction <xxx> identifies an absolute address referencing memory Signal displacement value, n bits wide (example: d16 is a 16-bit displacement Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) ...
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Instruction Set Summary Table 2-6. Notational Conventions (Continued) Instruction C Carry N Negative V Overflow X Extend Z Zero 2.6.1 Additions to the Instruction Set Architecture The original ColdFire instruction set architecture (ISA) was derived from the M68000 Family opcodes ...
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Enhancements to existing Revision_A instructions: — Longword support for branch instructions (Bcc, BRA, BSR) — Byte and word support for compare instructions (CMP, CMPI) — Word support for the compare address register instruction (CMPA) — Byte and longword support ...
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Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax ADDI #<data>,Dx ADDQ #<data>,<ea>x ADDX Dy,Dx AND Dy,<ea>x <ea>y,Dx ANDI #<data>,Dx ASL Dy,Dx #<data>,Dx ASR Dy,Dx #<data>,Dx Bcc <label> BCHG Dy,<ea>x #<data>,<ea-1>x BCLR Dy,<ea>x #<data>,<ea-1>x BRA <label> ...
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Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax LINK Ax,#<d16> LSL Dy,Dx #<data>,Dx LSR Dy,Dx #<data>,Dx MAC Ry,RxSF MACL Ry,RxSF,<ea-1>y,Rw MOV3Q #<data>,<ea>x MOVE <ea>y,<ea>x MOVE from MASK,Rx MAC ACC,Rx MACSR,Rx MACSR,CCR MOVE to Ry,ACC MAC Ry,MACSR Ry,MASK #<data>,ACC ...
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Instruction Set Summary Table 2-8. User-Level Instruction Set Summary (Continued) Instruction Operand Syntax NOP none NOT Dx OR <ea>y,Dx Dy,<ea>x ORI #<data>,Dx PEA <ea-3>y PULSE none REMS <ea-1>,Dx REMU <ea-1>,Dx RTS none SATS Dx Scc Dx SUB <ea>y,Dx Dy,<ea>x SUBA ...
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Table 2-9. Supervisor-Level Instruction Set Summary Instruction Operand Syntax Operand Size CPUSHL (An) 1 HALT none INTOUCH (Ay) MOVE from SR SR, Dx MOVE to SR Dy,SR #<data>,SR MOVEC Ry,Rc RTE None STOP #<data> WDEBUG <ea-2>y 1 The HALT instruction ...
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Execution Timings In this sequence, the second instruction is held for three cycles stalling for the multiply instruction to update d0. If consecutive instructions update a register and use that register as a base of index value with a scale ...
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MOVE Instruction Execution Timing Execution timing for the MOVE.{B,W,L} instructions are shown in the next tables. Table 2-13 shows the timing for the other generic move operations. For all tables in this section, the execution time of any instruction ...
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Execution Timings Table 2-12. Move Long Execution Times (Continued) Source Rx (Ax) -(Ay) 1(1/0) 2(1/1) (d16,Ay) 1(1/0) 2(1/1) (d8,Ay,Xi*SF) 2(1/0) 3(1/1) (xxx).w 1(1/0) 2(1/1) (xxx).l 1(1/0) 2(1/1) (d16,PC) 1(1/0) 2(1/1) (d8,PC,Xi*SF) 2(1/0) 3(1/1) #<xxx> 1(0/0) 1(0/1) Table 2-13 gives execution ...
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Table 2-14. One-Operand Instruction Execution Times Opcode <ea> Rn (An) clr.b <ea> 1(0/0) 1(0/1) clr.w <ea> 1(0/0) 1(0/1) clr.l <ea> 1(0/0) 1(0/1) ext.w Dx 1(0/0) ext.l Dx 1(0/0) extb.l Dx 1(0/0) neg.l Dx 1(0/0) negx.l Dx 1(0/0) not.l Dx 1(0/0) ...
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Execution Timings Table 2-15. Two-Operand Instruction Execution Times (Continued) Opcode <ea> Rn bchg #imm,<ea> 2(0/0) bclr Dy,<ea> 2(0/0) bclr #imm,<ea> 2(0/0) bset Dy,<ea> 2(0/0) bset #imm,<ea> 2(0/0) btst Dy,<ea> 2(0/0) btst #imm,<ea> 1(0/0) cmp.b <ea>,Rx 1(0/0) cmp.w <ea>,Rx 1(0/0) cmp.l ...
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Table 2-15. Two-Operand Instruction Execution Times (Continued) Opcode <ea> Rn or.l Dy,<ea> — or.l #imm,Dx 1(0/0) rems.l <ea>,Dx 35(0/0) remu.l <ea>,Dx 35(0/0) sub.l <ea>,Rx 1(0/0) sub.l Dy,<ea> — subi.l #imm,Dx 1(0/0) subq.l #imm,<ea> 1(0/0) subx.l Dy,Dx 1(0/0) 2.7.4 Miscellaneous Instruction ...
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Execution Timings Table 2-16. Miscellaneous Instruction Execution Times (Continued) Opcode <ea> Rn unlk Ax 1(1/0) wddata. <ea> — {b,w,l} wdebug.l <ea> — the number of registers moved by the MOVEM opcode 2 The execution time for STOP ...
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Exception Processing Overview Exception processing for ColdFire processors is streamlined for performance. Differences from previous M68000 Family processors include the following: • A simplified exception vector table • Reduced relocation capabilities using the vector base register • A single ...
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Exception Processing Overview defined by Motorola; the remaining 192 are user-defined interrupt vectors. Table 2-19. Exception Vector Assignments Vector Numbers Vector Offset (Hex) 0 000 1 004 2 008 3 00C 4 010 5 014 6–7 018–01C 8 020 9 ...
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A7→ Format FS[3–2] + 0x04 Figure 2-1. Exception Stack Frame Form The 16-bit format/vector word contains three unique fields: • Format field—This 4-bit field at the top of the system stack is always written with a ...
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Exception Processing Overview 2.8.2 Processor Exceptions Table 2-22 describes MCF5407 exceptions. Table 2-22. MCF5407 Exceptions Exception Access Error Access errors are reported only in conjunction with an attempted store to write-protected memory. Thus, access errors associated with instruction fetch or ...
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Table 2-22. MCF5407 Exceptions (Continued) Exception Debug Caused by a hardware breakpoint register trigger. Rather than generating an IACK cycle, the Interrupt processor internally calculates the vector number (12 or 13, depending on the type of breakpoint trigger). Additionally, the ...
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ColdFire Instruction Set Architecture Enhancements 2.9 ColdFire Instruction Set Architecture Enhancements This section describes the new opcodes implemented as part of the Revision B enhancements to the basic ColdFire ISA. In some cases, the opcodes represent minor enhancements to existing ...
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Bcc Operation: If Condition True Assembler Syntax: Bcc <label> Attributes: Size = byte, word, long Description: If the condition is true, execution continues at (PC) + displacement. PC holds the address of the instruction word for the Bcc instruction, plus ...
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ColdFire Instruction Set Architecture Enhancements BRA Operation Assembler Syntax: BRA <label> Attributes: Size = byte, word, long Description: Program execution continues at location (PC) + displacement. The PC contains the address of the instruction word of ...
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BSR Operation: SP – 4 → SP; PC → (SP Assembler Syntax: BSR <label> Attributes: Size = byte, word, long Description: Pushes the word address of the instruction immediately following the BSR instruction onto the system stack. ...
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ColdFire Instruction Set Architecture Enhancements CMP Operation: Destination – Source → cc Assembler Syntax: CMP <ea>y, Dx Attributes: Size = byte, word, long Description: Subtracts the source operand from the destination operand in the data register and sets condition codes ...
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CMPA Operation: Destination – Source → cc Assembler Syntax: CMPA <ea>y, Ax Attributes: Size = word, long Description: Operates similarly to CMP, but is used when the destination register is an address register rather than a data register. The operation ...
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ColdFire Instruction Set Architecture Enhancements CMPI Operation: Destination – Immediate Data → cc Assembler Syntax: CMPI #<data>, Dx Attributes: Size = byte, word, long Description: Operates similarly to CMP, but is used when the source operand is immediate data. The ...
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INTOUCH Operation: If Supervisor State else TRAP Assembler Syntax INTOUCH <Ay> Attributes: Unsized Description: Generates an instruction fetch reference at address (Ay). If the referenced address space is a cacheable region, this instruction can be used to prefetch a 16-byte ...
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ColdFire Instruction Set Architecture Enhancements MOVE Move Data from Source to Destination Operation: Source → Destination Assembler Syntax: MOVE <ea>y, <ea>x Attributes: Size = byte, word, long Description: Moves the data at the source to the destination location and sets ...
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Addressing Mode Mode Dy 000 reg. number:Dy Ay 001 reg. number:Ay (Ay) 010 reg. number:Ay (Ay) + 011 reg. number:Ay – (Ay) 100 reg. number:Ay (d ,Ay) 101 reg. number:Ay 16 Most assemblers use MOVEA when the destination is an ...
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ColdFire Instruction Set Architecture Enhancements MOVEA Move Address from Source to Destination Operation: Source → Destination Assembler Syntax: MOVEA <ea>y, Ax Attributes: Size = word, long Description: Moves the address at the source to the destination location and sets the ...
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MOV3Q Operation: Immediate Data → Destination Assembler Syntax MOV3Q #<data>,<ea>x Attributes: Size = long Description: Move the immediate data to the operand at the destination location. The data range is from - excluding 0. The immediate data is ...
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ColdFire Instruction Set Architecture Enhancements MVS Operation: (Source with sign extension) → Destination Assembler Syntax: MVS <ea>y,Dx Attributes: Size = byte, word Description: Sign-extend the source operand and move to the destination register. For the byte operation, bit 7 of ...
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MVZ Operation: (Source with zero fill) → Destination Assembler Syntax MVZ <ea>y,Dx Attributes: Size = byte, word Description—Zero-fill the source operand and move to the destination register. For the byte operation, the source operand is moved to bits 7–0 of ...
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ColdFire Instruction Set Architecture Enhancements SATS Operation: If CCR then if Dx[31 then Dx[31:0] = 0x80000000 else Dx[31:0] = 0x7FFFFFFF else Dx[31:0] is unchanged Assembler Syntax: SATS Dx Attributes: Size = long Description: Update the destination ...
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TAS Operation: Destination Tested → CCR; 1 → bit 7 of Destination Assembler Syntax: TAS <ea>x Attributes: Size = byte Description: Tests and sets the byte operand addressed by the effective address field. The instruction tests the current value of ...
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ColdFire Instruction Set Architecture Enhancements 2-52 MCF5407 User’s Manual ...
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Chapter 3 Hardware Multiply/Accumulate (MAC) Unit This chapter describes the MCF5407 multiply/accumulate (MAC) unit, which executes integer multiply, multiply-accumulate, and miscellaneous register instructions. The MAC is integrated into the operand execution pipeline (OEP). 3.1 Overview The MAC unit provides hardware ...
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Overview Figure 3-1. ColdFire MAC Multiplication and Accumulation The MAC unit is an extension of the basic multiplier found on most microprocessors. It can perform operations native to signal processing algorithms in an acceptable number of cycles, given the application ...
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These registers are described as follows: • Accumulator (ACC)—This 32-bit, read/write, general-purpose register is used to accumulate the results of MAC operations. • Mask register (MASK)—This 16-bit general-purpose register provides an optional address mask for MAC instructions that fetch operands ...
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Overview The need to move large amounts of data quickly can limit throughput in DSP engines. However, data can be moved efficiently by using the MOVEM instruction, which automatically generates line-sized burst references and is ideal for filling registers quickly ...
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Two’s complement unsigned integer: In this format, an N-bit operand represents a number within the range 0 < operand < 2 least significant bit. • Two’s complement, signed fractional N-bit number, the first bit is the sign ...
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MAC Instruction Execution Timings Table 3-3. MAC Move Instruction Execution Times Opcode <ea> Rn move.l <ea>,ACC 1(0/0) move.l <ea>,MACSR 6(0/0) move.l <ea>,MASK 5(0/0) move.l ACC,Rx 1(0/0) move.l MACSR,CCR 1(0/0) move.l MACSR,Rx 1(0/0) move.l MASK,Rx 1(0/0) 3-6 Effective Address (An) (An)+ ...
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Chapter 4 Local Memory This chapter describes the MCF5407 implementation of the ColdFire Version 4 local memory specification. It consists of two major sections. • Section 4.2, “SRAM Overview,” describes the MCF5407 on-chip static RAM (SRAM) implementation. It covers general ...
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SRAM Operation 0-modulo-2K location in the 4-Gbyte address space and configured to respond to either instruction or data accesses. Time-critical functions can be mapped into instruction memory and the system stack. Other heavily-referenced data can be mapped into data memory. ...
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Accesses are attempted in the following order: 1. SRAM 2. Cache (if space is defined as cacheable) 3. External access 4.4 SRAM Programming Model The SRAM programming model consists of RAMBAR0 and RAMBAR1. 4.4.1 SRAM Base Address Registers (RAMBAR0/RAMBAR1) The ...
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SRAM Initialization Table 4-1. RAMBARn Field Description (Continued) Bits Name 6 — Reserved, should be cleared. 5–1 C/I, Address space masks (ASn). These fields allow certain types of accesses to be masked, or SC, inhibited from accessing the SRAM module. ...
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Read the source data and write it to the SRAM. Various instructions support this function, including memory-to-memory move instructions and the move multiple instruction (MOVEM). MOVEM is optimized to generate line-sized burst fetches on line-aligned addresses generally ...
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Power Management ; +0 saved saved saved d4 ; +12 returnPc ; +16 pointer to source operand ; +20 destinationOffset ; +24 bytesToMove move.l RAMBASE+RAMFLAGS,a0 movec.l a0,rambar0 move.l 16(a7),a0 lea.l RAMBASE,a1 add.l 20(a7),a1 move.l ...
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The MCF5407 implements a special branch instruction cache for accelerating branches, enabled by a bit in the cache access control register (CACR[BEC]). The branch cache is described in Section 2.1.2.1.1, “Branch Acceleration.” The MCF5407 processor’s Harvard memory structure includes an ...
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Cache Organization 4.8 Cache Organization A four-way set associative cache is organized as four ways (levels). There are 128 sets in the 8-Kbyte data cache with each line containing 16 bytes (4 longwords). The 16-Kbyte instruction cache has 256 sets. ...
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The Cache at Start-Up As Figure 4-4 (A) shows, after power-up, cache contents are undefined; V and M may be set on some lines even though the cache may not contain the appropriate data for start up. Because reset ...
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Cache Organization Invalid ( Valid, not modified ( Valid, modified ( A:Cache population at start-up Way 0 Way 1 Way 2 Way 3 Set 0 Set 127 At ...
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Cache Operation Figure 4-5 shows the general fl caching operation using the 8-Kbyte data cache as an example. The discussion in this chapter assumes a data cache. Instruction cache operations are similar except that there is no ...
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Cache Operation To allocate a cache entry, the cache set index selects one of the cache’s 128 sets. The cache control logic looks for an invalid cache line to use for the new entry. If none is available, the cache ...
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Write accesses designated as cache-inhibited by the CACR or ACR bypass the cache and perform a corresponding external write. Normally, cache-inhibited reads bypass the cache and are performed on the external bus. The exception to this normal operation occurs when ...
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Cache Operation 4.9.1.1 Cacheable Accesses If ACRn[CM] or the default field of the CACR indicates write-through or copyback, the access is cacheable. A read access to a write-through or copyback region is read from the cache if matching data is ...
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In determining whether a memory location is cacheable or cache-inhibited, the CPU checks memory-control registers in the following order: 1. RAMBARs 2. ACR0 and ACR2 3. ACR1 and ACR3 access does not hit in the RAMBARs or ...
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Cache Operation 4.9.3.1 Read Miss A processor read that misses in the cache requests the cache controller to generate a bus transaction. This bus transaction reads the needed line from memory and supplies the required data to the processor core. ...
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Write Hit (Data Cache Only) The cache controller handles processor writes that hit in the data cache differently for write-through and copyback regions. For write hits to a write-through region, portions of cache lines corresponding to the size of ...
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Cache Operation 4.9.5.2 Cache Pushes Cache pushes occur for line replacement and as required for the execution of the CPUSHL instruction. To reduce the requested data’s latency in the new line, the modified line being replaced is temporarily placed in ...
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Supervisor instructions, ...
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Cache Operation Invalid ( Valid, not modified ( Valid, modified ( A:Ways 0 and 1 are filled. Ways 2 and 3 are invalid. Way 0 Way 1 Way ...
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Cache Registers This section describes the MCF5407 implementation of the Version 4 cache registers. 4.10.1 Cache Control Register (CACR) The CACR in Figure 4-8 contains bits for configuring the cache. It can be written by the MOVEC register instruction ...
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Cache Registers Table 4-4. CACR Field Descriptions (Continued) Bits Name 27 DHLCK Half-data cache lock mode 0 Normal operation. The cache allocates the lowest invalid way. If all ways are valid, the cache allocates the way pointed at by the ...
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Table 4-4. CACR Field Descriptions (Continued) Bits Name 11 IHLCK Instruction cache half-lock. 0 Normal operation. The cache allocates to the lowest invalid way; if all ways are valid, the cache allocates to the way pointed at by the round-robin ...
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Cache Management Field Address Base Reset Uninitialized R/W Rc ACR0: 0x004; ACR1: 0x005; ACR2: 0x006; ACR3: 0x007 1 Reserved in ACR2 and ACR3. Figure 4-9. Access Control Register Format (ACRn) Table 4-5 describes ACRn fields. I Table ...
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The privileged CPUSHL instruction supports cache management by selectively pushing and invalidating cache lines. The address register used with CPUSHL directly addresses the cache’s directory array. The CPUSHL instruction flushes a cache line. The value of CACR[DDPI,IDPI] determines whether CPUSHL ...
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Cache Management addq.l #1,d0 move.l d0,a0 cmpi.l #4,d0 bne setloop rts The following CACR loads assume the instruction cache has been invalidated, the default instruction cache mode is cacheable, and the default data cache mode is copyback. dataCacheLoadAndLock: move.l #0xa3080800,d0; ...
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A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache. ; lock it! move.l #0xa2088800,d0 movec d0,cacr rts 4.12 Cache Operation Summary This section gives operational details for ...
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Cache Operation Summary Table 4-6. Instruction Cache Line State Transitions (Continued) Access Invalid ( Cache II5 No action; invalidate stay in invalid state. Cache II6, No action; push II7 stay in invalid state. 4.12.2 Data Cache State Transitions ...
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Figure 4-14 shows the two possible states for a cache line in write-through mode. WI3—CPU write miss WI5—DCINVA WI6—CPUSHL & DDPI WI7—CPUSHL & DDPI Invalid Figure 4-14. Data Cache Line State Diagram—Write-Through Mode Table 4-7 describes data ...
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Cache Operation Summary Table 4-7. Data Cache Line State Transitions (Continued) Access Invalid ( Write hit WI4 Not possible. (write- through) Cache (C,W)I5 No action; invalidate stay in invalid state. Cache (C,W)I6 No action; push (C,W)I7 stay in ...
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Table 4-9. Data Cache Line State Transitions (Current State Valid) Access Read miss Read hit Write miss (copyback) Write miss (write-through) Write hit (copyback) Write hit (write-through) Cache invalidate Cache push Cache push In Table 4-10 the current state is ...
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Cache Initialization Code Table 4-10. Data Cache Line State Transitions (Current State Modified) (Continued) Access Cache invalidate CD5 No action (modified data lost invalid state. Cache push CD6 Push modified line to memory invalid state. Cache ...
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Chapter 5 Debug Support This chapter describes the Revision C enhanced hardware debug support in the MCF5407. This revision of the ColdFire debug architecture encompasses the two earlier revisions. 5.1 Overview The debug module is shown in Figure 5-1. ColdFire ...
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Signal Descriptions The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based on feedback from customers and third-party developers, enhancements have been added to succeeding generations of ColdFire cores. The Version 3 core implements the ...
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Figure 5-2 shows PSTCLK timing. PSTCLK PSTDDATA 5.2.1 Processor Status/Debug Data (PSTDDATA[7:0]) Processor status data outputs are used to indicate both processor status and captured address and data values. They operate at half the processor’s frequency. Given that real-time trace ...
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Real-Time Trace Support Table 5-3 shows the case where a PSTDDATA module captures a memory operand on a simple load instruction: mov.l <mem>,Rx. Table 5-3. PSTDDATA: Data Operand Captured Cycle T {PST for mov.l, PST marker for captured operand) = ...
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Execution speed is affected only when three storage elements have valid data to be dumped to the PSTDDATA port. This occurs only when two values are captured simultaneously in a read-modify-write operation; the core stalls until two FIFO entries are ...
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Real-Time Trace Support 5.3.1 Begin Execution of Taken Branch (PST = 0x5) PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on PSTDDATA depending on the CSR settings. CSR also ...
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Processor Stopped or Breakpoint State Change (PST = 0xE) The 0xE encoding is generated either as a one- or multiple-cycle issue as follows: • When the MCF5407 is stopped by a STOP instruction, this encoding appears in multiple-cycle format. ...
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Programming Model Two scenarios exist for data—0xFFFF_FFFF • marker occurs on the left nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xBF 0xFF 0xFF 0xFF 0xFX (X indicates that the next PST value is guaranteed to ...
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Note: Each debug register is accessed as a 32-bit register; shaded fields ...
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Programming Model Table 5-6. BDM/Breakpoint Registers (Continued) DRc[4–0] Register Name 0x07 Trigger definition register 0x08 Program counter breakpoint register 0x09 Program counter breakpoint mask register 0x0A–0x0B Reserved 0x0C Address breakpoint high register 0x0D Address breakpoint low register 0x0E Data breakpoint ...
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Field RM SZM TTM Reset R/W AATR and AATR1 are accessible in supervisor mode as debug control register 0x06 and 0x16 respectively, and using the WDEBUG instruction and through the BDM port using the DRc[4–0] Figure ...
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Programming Model 5.4.2 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1) The address breakpoint low and high registers (ABLR, ABLR1, ABHR, and ABHR1), Figure 5-7, define regions in the processor’s data address space that can be used as part of the trigger. These ...
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Field R SZ Reset R/W BAAR[R,SZ] are loaded directly from the BDM command; BAAR[TT,TM] can be programmed as debug control register 0x05 from the external development system. For compatibility with Rev. A, BAAR is loaded each time AATR ...
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Programming Model Table 5-11 describes CSR fields. Table 5-11. CSR Field Descriptions Bit Name 31–28 BSTAT Breakpoint status. Provides read-only status information concerning hardware breakpoints. Also output on PSTDDATA when it is not displaying PST or other processor data. BSTAT ...
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Table 5-11. CSR Field Descriptions (Continued) Bit Name 12–11 DDC Debug data control. Controls operand data capture for PSTDDATA, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word ...
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Programming Model 31 Field Reset R/W DBR and DBR1 are accessible in supervisor mode as debug control register 0x0E and 0x1E, using the WDEBUG instruction and through the BDM port using the DBMR and DBMR1 are accessible in supervisor mode ...
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TDR and/or XTDR are configured appropriately. PBR bits are masked by clearing corresponding PBMR bits. Results are compared with the processor’s program counter register, as defined in TDR and/or ...
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Programming Model 5.4.7 Trigger Definition Register (TDR) The TDR, shown in Table 5-13, configures the operation of the hardware breakpoint logic that corresponds with the ABHR/ABLR/AATR, PBR/PBR1/PBR2/PBR3/PBMR, and DBR/DBMR registers within the debug module. In conjunction with the XTDR and ...
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Table 5-17. TDR Field Descriptions Bits Name 31–30 TRC Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger response is always displayed on PSTDDATA. 00 Display on PSTDDATA only 01 Processor halt 10 Debug ...
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Programming Model The debug module has no hardware interlocks prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable TDR and XTDR (by clearing TDR[29,13] and XTDR[29,13]) before defining triggers. A write to the XTDR clears ...
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Table 5-18. XTDR Field Descriptions (Continued) Bits Name 21/5 DI Data breakpoint invert. Provides a way to invert the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value ...
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Background Debug Mode (BDM) then if (PC_breakpoint) if (Address_breakpoint then if (PC_breakpoint || Address1_breakpoint{&& Data1_breakpoint}) if (Address1_breakpoint then if (PC_breakpoint || Address_breakpoint{&& Data_breakpoint}) In this example, PC_breakpoint is the logical summation of the PBR/PBMR, PBR1, PBR2, and PBR3 breakpoint registers; ...
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The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction. If ...
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Background Debug Mode (BDM) • marker occurs on the right nibble of PSTDDATA with the data of 0xFF following: PSTDDATA[7:0] 0xYB 0xFF 0xFF 0xFF 0xFF 0xXY (X indicates that the PST value is guaranteed to not be 0xF; ...
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DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor CLK as well as the DSI. DSO is delayed from the DSCLK-enabled CLK rising edge (registered after ...
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Background Debug Mode (BDM) 5.5.2.2 Transmit Packet Format The basic transmit packet, Figure 5-17, consists of 16 data bits and 1 control bit Figure 5-17. Transmit BDM Packet Table 5-20 describes transmit BDM packet fields. Table 5-20. ...
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Table 5-21. BDM Command Summary (Continued) Command Mnemonic Output the _ Capture the current PC and display it on the SYNC PC current PC PSTDDATA output pins. Read control Read the system control register. RCREG register Write control Write the ...
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Background Debug Mode (BDM) Table 5-22. BDM Field Descriptions (Continued) Bit Name 7–6 Operand Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Size Note that a command performing a byte-sized memory read leaves the upper ...
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COMMANDS TRANSMITTED TO THE DEBUG MODULE COMMAND CODE TRANSMITTED DURING THIS CYCLE READ (LONG) MS ADDR ??? "NOT READY" XXX "ILLEGAL" SEQUENCE TAKEN IF ILLEGAL COMMAND IS RECEIVED BY DEBUG MODULE RESULTS FROM PREVIOUS COMMAND RESPONSES FROM THE DEBUG MODULE ...
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Background Debug Mode (BDM) • Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the ...
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Write A/D Register ( The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted. Command Format: ...
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Background Debug Mode (BDM) 5.5.3.3.3 Read Memory Location ( Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned ...
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Write Memory Location ( Write data to the memory location specified by the longword address. The address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses ...
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Background Debug Mode (BDM) Command Sequence: WRITE (B/W) MS ADDR ??? "NOT READY" WRITE (LONG) MS ADDR ??? "NOT READY" Figure 5-27. Operand Data This two-operand instruction requires a longword absolute address that specifies a location to which the data ...
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Dump Memory Block ( is used with the DUMP READ is executed to set up the starting address of the block and to retrieve the first result initial is not executed before the first READ The command ...
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Background Debug Mode (BDM) Command Sequence: DUMP (B/W) ??? DUMP (LONG) ??? Figure 5-29. Operand Data: None Result Data: Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word ...
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Fill Memory Block ( A command is used with the FILL initial is executed to set up the starting address of the block and to supply the first WRITE operand. The command writes subsequent operands. The initial address is ...
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Background Debug Mode (BDM) Command Sequence: FILL (LONG) FILL (B/W) MS DATA ??? "NOT READY" XXX "ILLEGAL" FILL (LONG) FILL (B/W) DATA ??? "NOT READY" XXX "ILLEGAL" Figure 5-31. Operand Data: A single operand is data to be written to ...
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Resume Execution ( The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is ...
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Background Debug Mode (BDM) 5.5.3.3.8 No Operation ( performs no operation and may be used as a null command where required. NOP Command Formats 0x0 Figure 5-34. Command Sequence: Figure 5-35. Operand Data: None Result Data: The ...
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Synchronize PC to the PSTDDATA Lines ( The _ command captures the current PC and displays it on the PSTDDATA outputs. SYNC PC After the debug module receives the command, it sends a signal to the ColdFire processor that ...
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Background Debug Mode (BDM) 5.5.3.3.10 Read Control Register ( Read the selected control register and return the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of ...
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Write Control Register ( The operand (longword) data is written to the specified control register. The write alters all 32 register bits. Command/Result Formats Command 0x2 0x0 0x0 Result Figure 5-40. Command Sequence: WCREG EXT WORD MS ...
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Background Debug Mode (BDM) 5.5.3.3.12 Read Debug Module Register ( Read the selected debug module register and return the 32-bit result. The only valid register selection for the command is CSR (DRc = 0x00). Note that this read of the ...