MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 276

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Asynchronous Operation
11.3.3 General Asynchronous Operation Guidelines
The DRAM controller provides control for RAS, CAS, and DRAMW signals, as well as
address multiplexing and bus cycle termination. Whether the mode is synchronous or
asynchronous determines signal control and termination. To reduce complexity,
multiplexing is the same for both modes. Table 11-6 shows the scheme for DRAM
configurations. This scheme works for symmetric configurations (in which the number of
rows equals the number of columns) as well as asymmetric configurations (in which the
number of rows and columns are different).
11-8
Bits
6–1
Address Pin
0
17
16
15
14
13
12
11
10
17
18
19
9
Name
AMx
V
Row Address
Address modifier masks. Determine which accesses can occur in a given DRAM block.
0 Allow access type to hit in DRAM
1 Do not allow access type to hit in DRAM
Valid. Cleared at reset to ensure that the DRAM block is not erroneously decoded.
0 Do not decode DRAM accesses.
1 Registers controlling the DRAM block are initialized; DRAM accesses can be decoded.
Table 11-5. DMR0/DMR1 Field Descriptions (Continued)
AM
SC
SD
UC
UD
Bit
C/I
17
16
15
14
13
12
11
10
17
18
19
Table 11-6. Generic Address Multiplexing Scheme
9
CPU space/interrupt acknowledge
Alternate master
Supervisor code
Supervisor data
User code
User data
Associated Access Type
Column Address
16
17
18
0
1
2
3
4
5
6
7
8
MCF5407 User’s Manual
8-bit port only
8- and 16-bit ports only
32-bit port only
16-bit port only or 32-bit port with only 8 column address lines
16-bit port only when at least 9 column address lines are used
Description
MOVEC instruction or interrupt acknowledge cycle
External or DMA master
Any supervisor-only instruction access
Any data fetched during the instruction access
Any user instruction
Any user data
Notes Relating to Port Sizes
Access Definition