MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 141

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Operation
4.9.3.4 Write Hit (Data Cache Only)
The cache controller handles processor writes that hit in the data cache differently for
write-through and copyback regions. For write hits to a write-through region, portions of
cache lines corresponding to the size of the access are updated with the data. The data is
also written to external memory. The cache line state is unchanged. For copyback accesses,
the cache controller updates the cache line and sets the M bit for the line. An external write
is not performed and the cache line state changes to (or remains in) the modified state.
4.9.4 Cache Coherency (Data Cache Only)
The MCF5407 provides limited cache coherency support in multiple-master environments.
Both write-through and copyback memory update techniques are supported to maintain
coherency between the cache and memory.
The cache does not support snooping (that is, cache coherency is not supported while
external or DMA masters are using the bus). Therefore, on-chip DMAs of the MCF5407
cannot access local memory and do not maintain coherency with the data cache.
4.9.5 Memory Accesses for Cache Maintenance
The cache controller performs all maintenance activities that supply data from the cache to
the core, including requests to the SIM for reading new cache lines and writing modified
lines to memory. The following sections describe memory accesses resulting from cache
fill and push operations. Chapter 18, “Bus Operation,” describes required bus cycles in
detail.
4.9.5.1 Cache Filling
When a new cache line is required, a line read is requested from the SIM, which generates
a burst-read transfer by indicating a line access with the size signals, SIZ[1:0].
The responding device supplies 4 consecutive longwords of data. Burst operations can be
inhibited or enabled through the burst read/write enable bits (BSTR/BSTW) in the
chip-select control registers (CSCR0–CSCR7).
SIM line accesses implicitly request burst-mode operations from memory. For more
information regarding external bus burst-mode accesses, see Chapter 18, “Bus Operation.”
The first cycle of a cache-line read loads the longword entry corresponding to the requested
address. Subsequent transfers load the remaining longword entries.
A burst operation is aborted by an a write-protection fault, which is the only possible access
error. Exception processing proceeds immediately. Note that unlike Version 2 and Version 3
access errors, the program counter stored on the exception stack frame points to the faulting
instruction. See Section 2.8.2, “Processor Exceptions.”
Chapter 4. Local Memory
4-17