MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 165

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

These registers are accessed through the BDM port by new BDM commands,
RDMREG
contain a 5-bit field, DRc, that specifies the register, as shown in Table 5-6.
Note: Each debug register is accessed as a 32-bit register; shaded fields above are not used (don’t care).
31
31
31
31
31
31
31
31
31
31
31
31
31
31
0x01–0x04 Reserved
DRc[4–0]
All debug control registers are writable from the external development system or the CPU via the
WDEBUG instruction.
CSR is write-only from the programming model as debug control register 0x00 using the supervisor-mode
WDEBUG instruction. It can be read from and written through the BDM port using the
WDMREG
0x00
0x05
0x06
, described in Section 5.5.3.3, “Command Set Descriptions.” These commands
commands.
Configuration/status register
BDM address attribute register
Address attribute trigger register
Figure 5-5. Debug Programming Model
15
15
15
15
15
15
15
15
15
15
15
15
15
15
Table 5-6. BDM/Breakpoint Registers
Register Name
Chapter 5. Debug Support
7
7
7
0
0
0
0
0
0
0
0
0
0
0
0
0
ABLR
ABHR
AATR1
ABLR1
ABHR1
BAAR
CSR
DBR
DBMR
DBR1
DBMR1
PBR
PBR1
PBR2
PBR3
PBMR
TDR
XTDR
AATR
Abbreviation
Address attribute trigger register
Address low breakpoint register
Address high breakpoint register
Address 1 attribute register
Address low breakpoint 1 register
Address high breakpoint 1 register
BDM address attribute register
Configuration/status register
Data breakpoint register
Data breakpoint mask register
Data breakpoint 1 register
Data breakpoint mask 1 register
PC breakpoint register
PC breakpoint 1 register
PC breakpoint 2 register
PC breakpoint 3 register
PC breakpoint mask register
Trigger definition register
Extended trigger definition register
BAAR
AATR
CSR
—
0x0020_0000
0x0000_0005
0x0000_0005
Initial State
—
Programming Model
RDMREG
WDMREG
and
p. 5-13
p. 5-12
p. 5-10
Page
—
and
5-9