MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 459

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In Figure 18-31, the external device is bus master during C1 and C2. During C2, the
MCF5407 requests the external bus because of a pending internal transfer. On C3, the
external releases mastership and the external arbiter grants the bus to the MCF5407 by
asserting BG. At this point, an internal is access pending so the MCF5407 asserts BD
during C4 and begins the access. Thus, the MCF5407 becomes the explicit bus master. Also
during C4, the external arbiter removes the grant from the MCF5407 by negating BG.
Because the MCF5407 is bus master, it continues to assert BD until the current transfer
completes. Because BG is negated, the MCF5407 negates BD during C9 and three-states
the external bus, thereby passing mastership to an external device.
The MCF5407 can assert BR to signal the external arbiter that it needs the bus. However,
there is no guarantee that when the bus is granted to the MCF5407 that a bus cycle will be
performed. At best, BR must be used as a status output that indicates when the MCF5407
needs the bus, but not as an indication that the MCF5407 is in a certain bus arbitration state.
Figure 18-32 is a high-level state diagram for MCF5407 bus arbitration protocol.
Table 18-6 describes the four states shown in Figure 18-32.
SIZ[1:0], TM[2:0]
A[31:0], TT[1:0]
D[31:0]
CLKIN
R/W
TIP
BG
AS
BR
BD
TS
TA
C1
Figure 18-31. Three-Wire Bus Arbitration
External
Master
C2
Chapter 18. Bus Operation
C3
C4
C5
General Operation of External Master Transfers
C6
MCF5407
C7
C8
C9
18-31