MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 461

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 18-11. Three-Wire Bus Arbitration Protocol Transition Conditions (Continued)
1
The bus arbitration state diagram can be used for the MCF5407 three-wire bus arbitration
protocol to approximate the high-level behavior of the MCF5407. It is assumed that all TS
or AS signals in a system are tied together and each bus device’s BD and BR signals are
connected individually to the external arbiter. The external arbiter must ensure that any
external masters will have released the bus after the next rising edge of CLKIN before
asserting BG to the MCF5407. The MCF5407 does not monitor external bus master
operation regarding bus arbitration.
18.10 Reset Operation
The MCF5407 supports two types of reset. Asserting RSTI resets the entire MCF5407. A
software watchdog reset resets everything but the internal PLL module.
Current
External
Both normal terminations and terminations due to bus errors generate an end of cycle. Bus cycles resulting from
a burst-inhibited transfer are considered part of that original transfer.
Explicit
master
master
State
Condition
Label
C1
C2
C3
C4
C5
D1
D2
D3
D4
The MCF5407 can start a transfer on the rising edge of CLKIN
the cycle after BG is asserted. The external arbiter should not
assert BG to the MCF5407 until the previous external master
stops driving the bus or the part may be damaged.
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
RSTI
Watchdog
Software
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Negated
Chapter 18. Bus Operation
Reset
NOTE:
Negated
Asserted
Asserted
Asserted
Asserted
Negated
Negated
Negated
Negated
BG
1
Asserted
Request
Negated
Bus
—
—
—
—
—
—
—
Progress
Transfer
Negated
Yes
Yes
—
—
—
—
—
—
in
Negated
Cycle
End of
Yes
—
—
—
—
—
—
—
Reset Operation
1
Next State
External
External
External
Explicit
Explicit
Explicit
Explicit
Explicit
master
master
master
master
master
master
master
Implicit
master
master
device
device
device
18-33