MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 160

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Real-Time Trace Support
Table 5-3 shows the case where a PSTDDATA module captures a memory operand on a
simple load instruction: mov.l <mem>,Rx.
A PST marker and its data display are transmitted contiguously. Except for this
transmission, the IDLE status (0x0) may appear any time. Again, given the real-time trace
information appears as a sequence of 4-bit values, there are no alignment restrictions. That
is, PST values and operands may appear on either nibble of PSTDDATA.
5.3 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug
function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This 8-bit port is partitioned
into two consecutive 4-bit nibbles. Each nibble can either transmit information concerning
the processor’s execution status (PST) or debug data (DDATA). The processor status may
not be related to the current bus transfer.
External development systems can use PSTDDATA outputs with an external image of the
program to completely track the dynamic execution path. This tracking is complicated by
any change in flow, especially when branch target address calculation is based on the
contents of a program-visible register (variant addressing). PSTDDATA outputs can be
configured to display the target address of such instructions in sequential nibble increments
across multiple processor clock cycles, as described in Section 5.3.1, “Begin Execution of
Taken Branch (PST = 0x5).” Four 32-bit storage elements form a FIFO buffer connecting
the processor’s high-speed local bus to the external development system through
PSTDDATA[7:0]. The buffer captures branch target addresses and certain data values for
eventual display on the PSTDDATA port, two nibbles at a time starting with the lsb.
5-4
Cycle
T+10
T+11
T+1
T+2
T+3
T+4
T+5
T+6
T+7
T+8
T+9
T
Table 5-3. PSTDDATA: Data Operand Captured
{PST for mov.l, PST marker for captured operand) = {0x1, 0xB}
{0x1, 0xB}
{Operand[3:0], Operand[7:4]}
{Operand[3:0], Operand[7:4]}
{Operand[11:8], Operand[15:12]}
{Operand[11:8], Operand[15:12]}
{Operand[19:16], Operand[23:20]}
{Operand[19:16], Operand[23:20]}
{Operand[27:24], Operand[31:28]}
{Operand[27:24], Operand[31:28]}
(PST for next instruction)
(PST for next instruction,...)
MCF5407 User’s Manual
PSTDDATA[7:0]