MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 263

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Provided the required address range is in the chip-select address register (CSAR0), CS0 can
be programmed to continue decoding for a range of addresses after the CSMR0[V] is set,
after which the global chip-select can be restored only by a system reset.
10.4 Chip-Select Registers
Table 10-7 is the chip-select register memory map. Reading reserved locations returns
zeros.
MBAR
0x0AC
Offset
0x08C
0x09C
0x0A0
0x0A4
0x0A8
0x0B0
0x0B4
0x080
0x084
0x088
0x090
0x094
0x098
Chip-select address register—bank 0 (CSAR0) [p. 10-6]
Chip-select address register—bank 1 (CSAR1) [p. 10-6]
Chip-select address register—bank 2 (CSAR2) [p. 10-6]
Chip-select address register—bank 3 (CSAR3) [p. 10-6]
Chip-select address register—bank 4 (CSAR4) [p. 10-6]
Table 10-6. D3/BE_CONFIG0, BE[3:0] Boot Configuration
D3/BE_CONFIG0
[31:24]
Table 10-5. D[6:5]/PS[1:0], Port Size of Boot CS0
0
1
D[6:5]/PS[1:0]
Table 10-7. Chip-Select Registers
Reserved
Reserved
Reserved
Reserved
Chip-select mask register—bank 0 (CSMR0) [p. 10-7]
Chip-select mask register—bank 1 (CSMR1) [p. 10-7]
Chip-select mask register—bank 2 (CSMR2) [p. 10-7]
Chip-select mask register—bank 3 (CSMR3) [p. 10-7]
Chip-select mask register—bank 4 (CSMR4) [p. 10-7]
Chapter 10. Chip-Select Module
00
01
1x
BE[3:0] is enabled as byte write enables only.
BE[3:0] is enabled as byte enables for reads and writes.
1
1
1
1
Configuration of Byte Enables for Boot CS0
[23:16]
Boot CS0 Port Size at Reset
32-bit port
16-bit port
8-bit port
Chip-select control register—bank 0
Chip-select control register—bank 1
Chip-select control register—bank 2
Chip-select control register—bank 3
[15:8]
(CSCR0) [p. 10-8]
(CSCR1) [p. 10-8]
(CSCR2) [p. 10-8]
(CSCR3) [p. 10-8]
Reserved
Reserved
Reserved
Reserved
Reserved
Chip-Select Registers
1
1
1
1
1
[7:0]
10-5