MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 50

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
WRITE Using Concurrent Auto Precharge
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(
Figure 31 on page 51 shows the nominal case and the extremes of
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is
applied after the last element of a completed burst. The new WRITE command should
be issued x cycles after the first WRITE command, where x equals BL/2.
Figure 32 on page 52 shows concatenated bursts of BL = 4. An example of nonconsecu-
tive WRITEs is shown in Figure 33 on page 52. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 34 on page 53. DDR2 SDRAM
supports concurrent auto precharge options, as shown in Table 10.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to
complete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated ONLY by another WRITE burst
as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architec-
ture of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or trun-
cated with any command except another WRITE command, as shown in Figure 35 on
page 53.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE,
cycles required to meet
WRITE burst may be followed by a subsequent PRECHARGE command.
met, as shown in Figure 37 on page 55.
of the data mask condition.
t
From Command
t
DQSS [MIN] and
WRITE with auto
DQSS.
precharge
(Bank n)
t
t
WTR should be met, as shown in Figure 36 on page 54. The number of clock
DQSS is specified with a relatively wide range (25 percent of one clock cycle).
t
READ or READ with auto
DQSS [MAX]) might not be intuitive, they have also been included.
PRECHARGE or ACTIVE
WRITE or WRITE with
t
auto precharge
To Command
WTR is either 2 or
precharge
(Bank m)
50
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WR starts at the end of the data burst, regardless
t
WTR/
Concurrent Auto Precharge)
512Mb: x4, x8, x16 DDR2 SDRAM
Minimum Delay (with
(CL - 1) + (BL/2) +
t
CK, whichever is greater. Data for any
(BL/2)
1
©2004 Micron Technology, Inc. All rights reserved.
t
t
DQSS for BL = 4. Upon
WTR
t
WR must be
t
DQSS.
WRITEs
Units
t
t
t
CK
CK
CK