MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 12

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 3:
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
A1, E1, M9, J9, R1 A1, E9, H9, L1
x16 FBGA Ball
G8, G2, H7, H3,
C8, C2, D7, D3,
C9, E9, G1, G3,
A7, B2, B8, D2,
H1, H9, F1, F9,
A9, C1, C3, C7,
D1, D9, B1, B9
A3, E3, J3, N1,
D8, E7, F2, F8,
Number
G7, G9
H2, H8
A2, E2
A8
B7
E8
P9
F7
J1
J2
J7
–
–
–
–
–
–
FBGA 84-/60-Ball Descriptions – 128 Meg x 4, 64 Meg x 8, 32 Meg x 16 (continued)
K8, K3, H2, K7,
H8, H3, H7, J2,
C8, C2, D7, D3,
D1, D9, B1, B9
B1, D1, D9, B9
Ball Number
A3, E3, J1, K9
x4, x8 FBGA
J8, J3, J7, K2,
C8,C2,D7,D3
B8, D2, D8
C3, C7, C9
A9, C1,
A7, B2,
B7, A8
L2, L8
B3
A2
E1
E2
E7
–
–
–
–
DQ12–DQ15
DQ8–DQ11
DQS, DQS#
DQ0–DQ3
DQ4–DQ7
DQ0–DQ3
DQ4–DQ7
DQ0–DQ3
A12–A13
Symbol
A8–A11
UDQS#
RDQS#
A0–A3
A4–A7
LDQS#
UDQS,
RDQS,
LDQS,
V
V
V
V
V
V
V
SS
DD
NC
NF
DD
SS
REF
DD
SS
DL
Q
Q
L
Output Redundant data strobe for 64 Meg x 8 only. RDQS is enabled/
Supply Power supply: 1.8V ±0.1V.
Supply DLL power supply: 1.8V ±0.1V.
Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved
Supply SSTL_18 reference voltage.
Supply Ground.
Supply DLL ground. Isolated on the device from V
Supply DQ ground. Isolated on the device for improved noise immunity.
Input Address inputs: Provide the row address for ACTIVE commands and
Type Description
I/O
I/O
I/O
I/O
I/O
I/O
–
–
the column address and auto precharge bit (A10) for READ/WRITE
commands to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA1–BA0) or all banks (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
command.
Data input/output: Bidirectional data bus for 32 Meg x 16.
Data input/output: Bidirectional data bus for 64 Meg x 8.
Data input/output: Bidirectional data bus for 128 Meg x 4.
Data strobe for upper byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used
when differential data strobe mode is enabled via the LOAD MODE
command.
Data strobe for lower byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read
data, center-aligned with write data. LDQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data, center
aligned with write data. DQS# is only used when differential data
strobe mode is enabled via the LOAD MODE command.
disabled via the LOAD MODE command to the extended mode
register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled,
ball B3 becomes data mask (see DM ball). RDQS# is only used when
RDQS is enabled and differential data strobe mode is enabled.
noise immunity.
No connect: These balls should be left unconnected.
No function: These balls are used as DQ4–DQ7 on the 64 Meg x 8,
but are NF (no function) on the 128 Meg x 4 configuration.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
©2004 Micron Technology, Inc. All rights reserved.
SS
and V
SS
Q.