MT47H64M8CB-3:B Micron Technology Inc, MT47H64M8CB-3:B Datasheet - Page 22

• Manufacturer Part Number: MT47H64M8CB-3:B
• Description: IC DDR2 SDRAM 512MBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc

Specifications of MT47H64M8CB-3:B

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 512M (64M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Down Mode
CAS Latency (CL)
PDF: 09005aef8117c18e, Source: 09005aef8211b2e6
512MbDDR2_2.fm - Rev. K 8/06 EN
Active power-down (PD) mode is defined by bit M12, as shown in Figure 8 on page 20.
PD mode allows the user to determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The
be enabled but “frozen” during active PD mode since the exit-to-READ command timing
is relaxed. The power difference expected between PD normal and PD low-power mode
is defined in the I
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 8 on page 20. CL is
the delay, in clock cycles, between the registration of a READ command and the avail-
ability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as unknown operation or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This
feature allows the READ command to be issued prior to
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
more detail in “Posted CAS Additive Latency (AL)” on page 26.
Examples of CL = 3 and CL = 4 are shown in Figure 9 on page 23; both assume AL = 0. If a
READ command is registered at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n + m (this assumes AL = 0).
t
XARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
t
XARDS parameter is used for slow-exit active PD exit timing. The DLL can
DD
table.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
t
RCD (MIN) by delaying the
Mode Register (MR)
©2004 Micron Technology, Inc. All rights reserved.